CN100472651C - 半导体存储装置 - Google Patents
半导体存储装置 Download PDFInfo
- Publication number
- CN100472651C CN100472651C CNB2004100973799A CN200410097379A CN100472651C CN 100472651 C CN100472651 C CN 100472651C CN B2004100973799 A CNB2004100973799 A CN B2004100973799A CN 200410097379 A CN200410097379 A CN 200410097379A CN 100472651 C CN100472651 C CN 100472651C
- Authority
- CN
- China
- Prior art keywords
- mentioned
- current potential
- electric power
- potential
- low electric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003398444A JP4249602B2 (ja) | 2003-11-28 | 2003-11-28 | 半導体記憶装置 |
JP2003398444 | 2003-11-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1627439A CN1627439A (zh) | 2005-06-15 |
CN100472651C true CN100472651C (zh) | 2009-03-25 |
Family
ID=34616573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100973799A Expired - Fee Related CN100472651C (zh) | 2003-11-28 | 2004-11-29 | 半导体存储装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7085187B2 (zh) |
JP (1) | JP4249602B2 (zh) |
CN (1) | CN100472651C (zh) |
DE (1) | DE102004055216A1 (zh) |
TW (1) | TWI253650B (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7499307B2 (en) * | 2005-06-24 | 2009-03-03 | Mosys, Inc. | Scalable embedded DRAM array |
US7274618B2 (en) * | 2005-06-24 | 2007-09-25 | Monolithic System Technology, Inc. | Word line driver for DRAM embedded in a logic process |
JP4255082B2 (ja) * | 2005-06-27 | 2009-04-15 | 富士通マイクロエレクトロニクス株式会社 | 電圧供給回路および半導体メモリ |
US20080030240A1 (en) * | 2006-08-04 | 2008-02-07 | Eric Scheuerlein | Low systematic offset, temperature independent voltage buffering |
JP4364260B2 (ja) * | 2007-05-28 | 2009-11-11 | 株式会社東芝 | 半導体記憶装置 |
US8391094B2 (en) | 2009-02-10 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits, systems, and operating methods thereof |
US8279686B2 (en) * | 2009-02-10 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits, systems, and methods for providing bit line equalization voltages |
WO2010119772A1 (ja) * | 2009-04-15 | 2010-10-21 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置およびそれを実装したicカード |
CN103310830B (zh) * | 2012-03-12 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | 字线驱动电路及存储器电路 |
US10636470B2 (en) | 2018-09-04 | 2020-04-28 | Micron Technology, Inc. | Source follower-based sensing scheme |
US10937476B2 (en) * | 2019-06-24 | 2021-03-02 | Micron Technology, Inc. | Apparatuses and methods for controlling word line discharge |
JP2021047969A (ja) * | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | メモリデバイス |
US11289134B2 (en) | 2019-10-23 | 2022-03-29 | Semiconductor Components Industries, Llc | Non-volatile memory reading circuits and methods for reducing sensing delay periods |
TWI749888B (zh) * | 2020-11-20 | 2021-12-11 | 智原科技股份有限公司 | 雙倍資料率記憶體系統及相關的閘信號控制電路 |
US11990175B2 (en) | 2022-04-01 | 2024-05-21 | Micron Technology, Inc. | Apparatuses and methods for controlling word line discharge |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5499211A (en) | 1995-03-13 | 1996-03-12 | International Business Machines Corporation | Bit-line precharge current limiter for CMOS dynamic memories |
JPH11126498A (ja) | 1997-10-22 | 1999-05-11 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JP2001052476A (ja) * | 1999-08-05 | 2001-02-23 | Mitsubishi Electric Corp | 半導体装置 |
JP3425916B2 (ja) | 1999-12-27 | 2003-07-14 | Necエレクトロニクス株式会社 | 半導体記憶装置 |
US6418075B2 (en) * | 2000-07-21 | 2002-07-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor merged logic and memory capable of preventing an increase in an abnormal current during power-up |
JP2003036676A (ja) | 2001-07-19 | 2003-02-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
-
2003
- 2003-11-28 JP JP2003398444A patent/JP4249602B2/ja not_active Expired - Fee Related
-
2004
- 2004-11-16 DE DE102004055216A patent/DE102004055216A1/de not_active Withdrawn
- 2004-11-16 TW TW093135075A patent/TWI253650B/zh not_active IP Right Cessation
- 2004-11-24 US US10/995,465 patent/US7085187B2/en not_active Expired - Fee Related
- 2004-11-29 CN CNB2004100973799A patent/CN100472651C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1627439A (zh) | 2005-06-15 |
DE102004055216A1 (de) | 2005-07-07 |
US7085187B2 (en) | 2006-08-01 |
JP2005158200A (ja) | 2005-06-16 |
TW200532688A (en) | 2005-10-01 |
US20050117411A1 (en) | 2005-06-02 |
JP4249602B2 (ja) | 2009-04-02 |
TWI253650B (en) | 2006-04-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: PS4 LASCO CO., LTD. Free format text: FORMER OWNER: NIHITATSU MEMORY CO., LTD. Effective date: 20130826 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130826 Address after: Luxemburg Luxemburg Patentee after: ELPIDA MEMORY INC. Address before: Tokyo, Japan Patentee before: Nihitatsu Memory Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090325 Termination date: 20151129 |