CN1004594B - 水平结构晶体管及其制作方法 - Google Patents

水平结构晶体管及其制作方法 Download PDF

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Publication number
CN1004594B
CN1004594B CN85108008.1A CN85108008A CN1004594B CN 1004594 B CN1004594 B CN 1004594B CN 85108008 A CN85108008 A CN 85108008A CN 1004594 B CN1004594 B CN 1004594B
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CN
China
Prior art keywords
region
island
epitaxial
epitaxial island
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CN85108008.1A
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English (en)
Chinese (zh)
Other versions
CN85108008A (zh
Inventor
戴维·B·斯伯特
詹姆斯·D·琼拉瑞
爱尔顿·J·赞雷斯基
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN85108008A publication Critical patent/CN85108008A/zh
Publication of CN1004594B publication Critical patent/CN1004594B/zh
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/041—Manufacture or treatment of thin-film BJTs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/60—Lateral BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
CN85108008.1A 1984-10-31 1985-10-30 水平结构晶体管及其制作方法 Expired CN1004594B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66694284A 1984-10-31 1984-10-31
US666,942 1984-10-31

Publications (2)

Publication Number Publication Date
CN85108008A CN85108008A (zh) 1986-05-10
CN1004594B true CN1004594B (zh) 1989-06-21

Family

ID=24676160

Family Applications (1)

Application Number Title Priority Date Filing Date
CN85108008.1A Expired CN1004594B (zh) 1984-10-31 1985-10-30 水平结构晶体管及其制作方法

Country Status (4)

Country Link
EP (1) EP0180363B1 (enExample)
JP (1) JPS61180481A (enExample)
CN (1) CN1004594B (enExample)
DE (1) DE3587797T2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0812865B2 (ja) * 1989-06-06 1996-02-07 株式会社東芝 バイポーラトランジスタとその製造方法
JP3190057B2 (ja) * 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
US5994739A (en) * 1990-07-02 1999-11-30 Kabushiki Kaisha Toshiba Integrated circuit device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3174777D1 (en) * 1980-10-23 1986-07-10 Fairchild Camera Instr Co Method of fabricating integrated circuit structure
EP0059264A1 (en) * 1981-03-02 1982-09-08 Rockwell International Corporation NPN Type lateral transistor with minimal substrate operation interference and method for producing same
EP0068073A2 (en) * 1981-07-01 1983-01-05 Rockwell International Corporation PNP type lateral transistor with minimal substrate operation interference and method for producing same
JPS5852817A (ja) * 1981-09-25 1983-03-29 Hitachi Ltd 半導体装置及びその製造方法
EP0144654A3 (en) * 1983-11-03 1987-10-07 General Electric Company Semiconductor device structure including a dielectrically-isolated insulated-gate transistor

Also Published As

Publication number Publication date
EP0180363A2 (en) 1986-05-07
DE3587797D1 (de) 1994-05-19
EP0180363B1 (en) 1994-04-13
EP0180363A3 (en) 1987-12-02
CN85108008A (zh) 1986-05-10
DE3587797T2 (de) 1994-07-28
JPS61180481A (ja) 1986-08-13
JPH0523495B2 (enExample) 1993-04-02

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GR02 Examined patent application
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GR01 Patent grant
C17 Cessation of patent right
CX01 Expiry of patent term