JPH0244154B2 - - Google Patents

Info

Publication number
JPH0244154B2
JPH0244154B2 JP59005862A JP586284A JPH0244154B2 JP H0244154 B2 JPH0244154 B2 JP H0244154B2 JP 59005862 A JP59005862 A JP 59005862A JP 586284 A JP586284 A JP 586284A JP H0244154 B2 JPH0244154 B2 JP H0244154B2
Authority
JP
Japan
Prior art keywords
layer
well
mask
oxide
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59005862A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59204232A (ja
Inventor
Hyu Jendaajeemuzu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS59204232A publication Critical patent/JPS59204232A/ja
Publication of JPH0244154B2 publication Critical patent/JPH0244154B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W10/13—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P76/40—
    • H10W10/0127—

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
JP59005862A 1983-05-02 1984-01-18 相補形ｍｏｓ構造体の形成方法 Granted JPS59204232A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US490766 1983-05-02
US06/490,766 US4471523A (en) 1983-05-02 1983-05-02 Self-aligned field implant for oxide-isolated CMOS FET

Publications (2)

Publication Number Publication Date
JPS59204232A JPS59204232A (ja) 1984-11-19
JPH0244154B2 true JPH0244154B2 (enExample) 1990-10-02

Family

ID=23949374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59005862A Granted JPS59204232A (ja) 1983-05-02 1984-01-18 相補形ｍｏｓ構造体の形成方法

Country Status (4)

Country Link
US (1) US4471523A (enExample)
EP (1) EP0127335B1 (enExample)
JP (1) JPS59204232A (enExample)
DE (1) DE3465828D1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536945A (en) * 1983-11-02 1985-08-27 National Semiconductor Corporation Process for producing CMOS structures with Schottky bipolar transistors
US4598460A (en) * 1984-12-10 1986-07-08 Solid State Scientific, Inc. Method of making a CMOS EPROM with independently selectable thresholds
US4662061A (en) * 1985-02-27 1987-05-05 Texas Instruments Incorporated Method for fabricating a CMOS well structure
US4685194A (en) * 1985-10-21 1987-08-11 The United States Of America As Represented By The Secretary Of The Air Force Direct moat self-aligned field oxide technique
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
US5045898A (en) 1988-08-30 1991-09-03 At&T Bell Laboratories CMOS integrated circuit having improved isolation
US4895520A (en) * 1989-02-02 1990-01-23 Standard Microsystems Corporation Method of fabricating a submicron silicon gate MOSFETg21 which has a self-aligned threshold implant
DE69030822T2 (de) 1989-02-14 1997-11-27 Seiko Epson Corp Halbleitervorrichtung und Verfahren zu ihrer Herstellung
US5132236A (en) * 1991-07-30 1992-07-21 Micron Technology, Inc. Method of semiconductor manufacture using an inverse self-aligned mask
US6071775A (en) * 1997-02-21 2000-06-06 Samsung Electronics Co., Ltd. Methods for forming peripheral circuits including high voltage transistors with LDD structures
US6040604A (en) * 1997-07-21 2000-03-21 Motorola, Inc. Semiconductor component comprising an electrostatic-discharge protection device
CN1219328C (zh) * 1998-02-19 2005-09-14 国际商业机器公司 具有改善了注入剂的场效应晶体管及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1503017A (en) * 1974-02-28 1978-03-08 Tokyo Shibaura Electric Co Method of manufacturing semiconductor devices
US4217149A (en) * 1976-09-08 1980-08-12 Sanyo Electric Co., Ltd. Method of manufacturing complementary insulated gate field effect semiconductor device by multiple implantations and diffusion
US4135955A (en) * 1977-09-21 1979-01-23 Harris Corporation Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation
US4313768A (en) * 1978-04-06 1982-02-02 Harris Corporation Method of fabricating improved radiation hardened self-aligned CMOS having Si doped Al field gate
JPS5529116A (en) * 1978-08-23 1980-03-01 Hitachi Ltd Manufacture of complementary misic
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate
US4282648A (en) * 1980-03-24 1981-08-11 Intel Corporation CMOS process
JPS5779667A (en) * 1980-11-05 1982-05-18 Fujitsu Ltd Manufacture of semiconductor device
US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
JPS5810857A (ja) * 1981-07-10 1983-01-21 Nec Corp 相補型ｍｏｓ半導体装置
JPS5817657A (ja) * 1981-07-24 1983-02-01 Hitachi Ltd 半導体装置
US4385947A (en) * 1981-07-29 1983-05-31 Harris Corporation Method for fabricating CMOS in P substrate with single guard ring using local oxidation
US4411058A (en) * 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband

Also Published As

Publication number Publication date
US4471523A (en) 1984-09-18
JPS59204232A (ja) 1984-11-19
EP0127335B1 (en) 1987-09-02
DE3465828D1 (en) 1987-10-08
EP0127335A1 (en) 1984-12-05

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