DE3465828D1 - Method of forming contiguous self-aligned implanted semiconductor regions and method of forming an integrated cmos structure - Google Patents
Method of forming contiguous self-aligned implanted semiconductor regions and method of forming an integrated cmos structureInfo
- Publication number
- DE3465828D1 DE3465828D1 DE8484302894T DE3465828T DE3465828D1 DE 3465828 D1 DE3465828 D1 DE 3465828D1 DE 8484302894 T DE8484302894 T DE 8484302894T DE 3465828 T DE3465828 T DE 3465828T DE 3465828 D1 DE3465828 D1 DE 3465828D1
- Authority
- DE
- Germany
- Prior art keywords
- forming
- semiconductor regions
- cmos structure
- integrated cmos
- implanted semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/490,766 US4471523A (en) | 1983-05-02 | 1983-05-02 | Self-aligned field implant for oxide-isolated CMOS FET |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3465828D1 true DE3465828D1 (en) | 1987-10-08 |
Family
ID=23949374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484302894T Expired DE3465828D1 (en) | 1983-05-02 | 1984-04-30 | Method of forming contiguous self-aligned implanted semiconductor regions and method of forming an integrated cmos structure |
Country Status (4)
Country | Link |
---|---|
US (1) | US4471523A (de) |
EP (1) | EP0127335B1 (de) |
JP (1) | JPS59204232A (de) |
DE (1) | DE3465828D1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4536945A (en) * | 1983-11-02 | 1985-08-27 | National Semiconductor Corporation | Process for producing CMOS structures with Schottky bipolar transistors |
US4598460A (en) * | 1984-12-10 | 1986-07-08 | Solid State Scientific, Inc. | Method of making a CMOS EPROM with independently selectable thresholds |
US4662061A (en) * | 1985-02-27 | 1987-05-05 | Texas Instruments Incorporated | Method for fabricating a CMOS well structure |
US4685194A (en) * | 1985-10-21 | 1987-08-11 | The United States Of America As Represented By The Secretary Of The Air Force | Direct moat self-aligned field oxide technique |
EP0313683A1 (de) * | 1987-10-30 | 1989-05-03 | International Business Machines Corporation | Verfahren zur Herstellung einer halbleitenden integrierten Schaltungsstruktur, die ein submikrometrisches Bauelement enthält |
US5045898A (en) | 1988-08-30 | 1991-09-03 | At&T Bell Laboratories | CMOS integrated circuit having improved isolation |
US4895520A (en) * | 1989-02-02 | 1990-01-23 | Standard Microsystems Corporation | Method of fabricating a submicron silicon gate MOSFETg21 which has a self-aligned threshold implant |
DE69030822T2 (de) * | 1989-02-14 | 1997-11-27 | Seiko Epson Corp | Halbleitervorrichtung und Verfahren zu ihrer Herstellung |
US5132236A (en) * | 1991-07-30 | 1992-07-21 | Micron Technology, Inc. | Method of semiconductor manufacture using an inverse self-aligned mask |
US6071775A (en) * | 1997-02-21 | 2000-06-06 | Samsung Electronics Co., Ltd. | Methods for forming peripheral circuits including high voltage transistors with LDD structures |
US6040604A (en) * | 1997-07-21 | 2000-03-21 | Motorola, Inc. | Semiconductor component comprising an electrostatic-discharge protection device |
CN1219328C (zh) * | 1998-02-19 | 2005-09-14 | 国际商业机器公司 | 具有改善了注入剂的场效应晶体管及其制造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1503017A (en) * | 1974-02-28 | 1978-03-08 | Tokyo Shibaura Electric Co | Method of manufacturing semiconductor devices |
US4217149A (en) * | 1976-09-08 | 1980-08-12 | Sanyo Electric Co., Ltd. | Method of manufacturing complementary insulated gate field effect semiconductor device by multiple implantations and diffusion |
US4135955A (en) * | 1977-09-21 | 1979-01-23 | Harris Corporation | Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation |
US4313768A (en) * | 1978-04-06 | 1982-02-02 | Harris Corporation | Method of fabricating improved radiation hardened self-aligned CMOS having Si doped Al field gate |
JPS5529116A (en) * | 1978-08-23 | 1980-03-01 | Hitachi Ltd | Manufacture of complementary misic |
IT1166587B (it) * | 1979-01-22 | 1987-05-05 | Ates Componenti Elettron | Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate |
US4282648A (en) * | 1980-03-24 | 1981-08-11 | Intel Corporation | CMOS process |
JPS5779667A (en) * | 1980-11-05 | 1982-05-18 | Fujitsu Ltd | Manufacture of semiconductor device |
US4374700A (en) * | 1981-05-29 | 1983-02-22 | Texas Instruments Incorporated | Method of manufacturing silicide contacts for CMOS devices |
JPS5810857A (ja) * | 1981-07-10 | 1983-01-21 | Nec Corp | 相補型mos半導体装置 |
JPS5817657A (ja) * | 1981-07-24 | 1983-02-01 | Hitachi Ltd | 半導体装置 |
US4385947A (en) * | 1981-07-29 | 1983-05-31 | Harris Corporation | Method for fabricating CMOS in P substrate with single guard ring using local oxidation |
US4411058A (en) * | 1981-08-31 | 1983-10-25 | Hughes Aircraft Company | Process for fabricating CMOS devices with self-aligned channel stops |
US4412375A (en) * | 1982-06-10 | 1983-11-01 | Intel Corporation | Method for fabricating CMOS devices with guardband |
-
1983
- 1983-05-02 US US06/490,766 patent/US4471523A/en not_active Expired - Lifetime
-
1984
- 1984-01-18 JP JP59005862A patent/JPS59204232A/ja active Granted
- 1984-04-30 EP EP84302894A patent/EP0127335B1/de not_active Expired
- 1984-04-30 DE DE8484302894T patent/DE3465828D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0127335A1 (de) | 1984-12-05 |
EP0127335B1 (de) | 1987-09-02 |
US4471523A (en) | 1984-09-18 |
JPH0244154B2 (de) | 1990-10-02 |
JPS59204232A (ja) | 1984-11-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |