CN100452385C - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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Publication number
CN100452385C
CN100452385C CNB2005100644921A CN200510064492A CN100452385C CN 100452385 C CN100452385 C CN 100452385C CN B2005100644921 A CNB2005100644921 A CN B2005100644921A CN 200510064492 A CN200510064492 A CN 200510064492A CN 100452385 C CN100452385 C CN 100452385C
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CN
China
Prior art keywords
covering layer
metal
layer
insulating layer
cover layer
Prior art date
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Expired - Lifetime
Application number
CNB2005100644921A
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English (en)
Chinese (zh)
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CN1734760A (zh
Inventor
李显铭
林俊成
潘兴强
谢静华
彭兆贤
黄震麟
苏莉玲
眭晓林
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN1734760A publication Critical patent/CN1734760A/zh
Application granted granted Critical
Publication of CN100452385C publication Critical patent/CN100452385C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
CNB2005100644921A 2004-08-03 2005-04-18 半导体元件及其制造方法 Expired - Lifetime CN100452385C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/909,980 2004-08-03
US10/909,980 US7253501B2 (en) 2004-08-03 2004-08-03 High performance metallization cap layer

Publications (2)

Publication Number Publication Date
CN1734760A CN1734760A (zh) 2006-02-15
CN100452385C true CN100452385C (zh) 2009-01-14

Family

ID=35756619

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB2005100644921A Expired - Lifetime CN100452385C (zh) 2004-08-03 2005-04-18 半导体元件及其制造方法
CNU2005200168507U Expired - Lifetime CN2793923Y (zh) 2004-08-03 2005-04-18 半导体元件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNU2005200168507U Expired - Lifetime CN2793923Y (zh) 2004-08-03 2005-04-18 半导体元件

Country Status (4)

Country Link
US (1) US7253501B2 (enExample)
JP (1) JP2006049896A (enExample)
CN (2) CN100452385C (enExample)
TW (1) TWI251300B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247946B2 (en) * 2005-01-18 2007-07-24 International Business Machines Corporation On-chip Cu interconnection using 1 to 5 nm thick metal cap
KR100808601B1 (ko) * 2006-12-28 2008-02-29 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
DE102007004867B4 (de) 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid
US8525339B2 (en) 2011-07-27 2013-09-03 International Business Machines Corporation Hybrid copper interconnect structure and method of fabricating same
US9312203B2 (en) 2013-01-02 2016-04-12 Globalfoundries Inc. Dual damascene structure with liner
US9490209B2 (en) * 2013-03-13 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Electro-migration barrier for Cu interconnect
US20150087144A1 (en) * 2013-09-26 2015-03-26 Taiwan Semiconductor Manufacturing Company Ltd. Apparatus and method of manufacturing metal gate semiconductor device
US9659857B2 (en) 2013-12-13 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method making the same
US20150206798A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure And Method of Forming
US9437484B2 (en) * 2014-10-17 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Etch stop layer in integrated circuits
CN108573942B (zh) * 2017-03-09 2021-09-14 联华电子股份有限公司 内连线结构及其制作方法
US11075113B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Metal capping layer and methods thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892281A (en) * 1996-06-10 1999-04-06 Micron Technology, Inc. Tantalum-aluminum-nitrogen material for semiconductor devices
CN1259762A (zh) * 1999-01-04 2000-07-12 国际商业机器公司 增强无机介质与铜的粘附性的等离子体处理
CN1057868C (zh) * 1995-03-04 2000-10-25 现代电子产业株式会社 形成半导体器件金属互连的方法
US6376371B1 (en) * 1997-03-31 2002-04-23 Motorola, Inc. Method of forming a semiconductor device
CN1402333A (zh) * 2001-08-29 2003-03-12 富士通株式会社 半导体设备及其制造方法
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6074960A (en) * 1997-08-20 2000-06-13 Micron Technology, Inc. Method and composition for selectively etching against cobalt silicide
US6727588B1 (en) 1999-08-19 2004-04-27 Agere Systems Inc. Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
US6165891A (en) 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
JP3851752B2 (ja) * 2000-03-27 2006-11-29 株式会社東芝 半導体装置の製造方法
US6709874B2 (en) 2001-01-24 2004-03-23 Infineon Technologies Ag Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation
US6680500B1 (en) 2002-07-31 2004-01-20 Infineon Technologies Ag Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers
US7105429B2 (en) * 2004-03-10 2006-09-12 Freescale Semiconductor, Inc. Method of inhibiting metal silicide encroachment in a transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1057868C (zh) * 1995-03-04 2000-10-25 现代电子产业株式会社 形成半导体器件金属互连的方法
US5892281A (en) * 1996-06-10 1999-04-06 Micron Technology, Inc. Tantalum-aluminum-nitrogen material for semiconductor devices
US6376371B1 (en) * 1997-03-31 2002-04-23 Motorola, Inc. Method of forming a semiconductor device
CN1259762A (zh) * 1999-01-04 2000-07-12 国际商业机器公司 增强无机介质与铜的粘附性的等离子体处理
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
CN1402333A (zh) * 2001-08-29 2003-03-12 富士通株式会社 半导体设备及其制造方法

Also Published As

Publication number Publication date
CN1734760A (zh) 2006-02-15
JP2006049896A (ja) 2006-02-16
CN2793923Y (zh) 2006-07-05
TWI251300B (en) 2006-03-11
US20060027922A1 (en) 2006-02-09
US7253501B2 (en) 2007-08-07
TW200607042A (en) 2006-02-16

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