CN100444372C - 半导体封装及其制造方法 - Google Patents
半导体封装及其制造方法 Download PDFInfo
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Abstract
本发明提供一种具有高频特性并且能获得大面积的内布线图案的半导体封装。根据本发明,一种半导体封装包括:多层印刷布线板12;和安装在多层印刷布线板12的正面上的IC芯片,以及多个安装在背面上的凸起端子16。每个凸起端子16包括具有平坦面40的绝缘芯部42以及淀积在除了平坦面40之外的所有外表面上的导电涂层。导电涂层44的端面类似于绝缘芯部42周围的环,并且焊接至形成于多层印刷布线板12的背面上的环形连接焊盘52。通路36紧邻的布置在凸起端子16之上,并且直径比凸起端子16的直径小的隙孔34形成于内布线图案28和30中以允许通路36通过。
Description
技术领域
本发明涉及半导体封装及其制造方法,并且更具体地,涉及其中集成电路芯片安装在多层印刷布线板上的半导体封装。
背景技术
表面安装技术发展的一个结果是其中集成电路芯片(下文中称为IC芯片)直接安装在多层印刷布线板的正面上的半导体封装的后续发展。在包括BGA(球栅阵列)的半导体封装中,多凸起端子的栅形阵列接合至多层布线板的背面(与正面即IC芯片安装面相反)。在这些凸起端子处,半导体封装焊接到母板(另一印刷布线板)。图34给出了接合至多层印刷布线板的凸起端子的一个举例的常规结构。
在图34中,凸起端子2,通常称为焊球,形成于多层印刷布线板1的背面上并且附接至盘形BGA焊盘3。BGA焊盘3通过直接位于焊球2上面的通路4连接至IC芯片(未示出)。其中容纳通路4的隙孔6形成于内布线图案5中。
为了容纳通路4,隙孔6的直径必须仅仅是稍大于通路4的直径。然而,在隙孔6的直径小于BGA焊盘3并且内布线图案5在BGA焊盘3之上向上延伸时,BGA焊盘3和内布线图案之间的寄生电容就增大并且高频特性就劣化。因而,高频特性偶尔通过将隙孔6的直径扩大为大于BGA焊盘3的直径而改进。
然而,由于具有很多BGA焊盘3,如果隙孔6的直径增大,那么内布线图案5可用的面积就小多了。并且尤其是如果减少了可用于电源或接地布线图案的面积,那么会不利地影响供电并且电压将会不稳定。
在日本未审专利公开说明书(Kokai)No.2005-5568(专利文献1)中公开了与适合的凸起结构位置、凸起的形状和尺寸以及制造方法相关的发明。形成于绝缘层上的这种凸起结构包括:通过液体材料的固化产生的凸形树脂部;以及覆盖该凸部的导电层。为了产生凸部,在绝缘层的顶面上形成斥液部和具有高度吸液性的亲液部,并且通过液体的萃取来固化亲液部(参见专利文献1的摘要)。这种凸起结构形成于布线板上以将布线板电连接至IC芯片(参见专利文献1的[0084]至[0086]段)。
凸起结构是用来将印刷布线板和IC芯片连接起来的凸起端子,并不用来将用于半导体封装的多层印刷布线板和母板(印刷电路板)连接起来。理论上,不可能用这种凸起结构的制造方法在凸部和绝缘层之间形成布线图案,并且因此,布线图案的面积受到限制。而且,专利文献1中并没有公开印刷布线板结构。
[专利文献1]
日本未审专利公开说明书(Kokai)No.2005-5568
发明内容
[本发明要解决的问题]
本发明的目的是提供一种具有超高频特性的半导体封装及其制造方法。
本发明的另一目的是提供一种具有大面积可供内布线图案使用的半导体封装,及其制造方法。
[解决问题的方式和本发明的优点]
根据本发明的一种半导体封装包括:印刷布线板、集成电路芯片和多个凸起端子。集成电路芯片安装在印刷布线板的正面上并且凸起端子安装在印刷布线板的背面上。每个凸起端子具有绝缘芯部并且涂覆有导体。绝缘芯部具有朝向印刷布线板背面的平坦面。导电涂层形成于凸起端子除了绝缘芯部的平坦面之外的外表面上,并且接合至印刷布线板的背面的环形连接焊盘上。
根据这种半导体封装,由于仅仅导电涂层的边缘暴露于绝缘芯部的平坦面周围,降低了寄生电容并且改进了高频特性。
优选地,印刷布线板包括绝缘板、正面布线图案、内布线图案、背面布线图案和通路。正面布线图案形成于绝缘板的正面上并且电连接至集成电路芯片。内布线图案制造有隙孔,并且嵌入在绝缘板中,而且背面布线图案形成于绝缘板的背面上并且电连接至凸起端子,该背面布线图案包括所述环形连接焊盘,而通路装配入隙孔中并电连接至背面布线图案。还优选地,背面布线图案包括通路连接盘,该通路连接盘设在预定位置,与绝缘芯部的平坦面相对,并且电连接至环形连接焊盘。通路和隙孔布置在通路连接盘上,并且优选地隙孔的直径小于绝缘芯部的平坦面的直径。利用这种布置,抑制了高频特性的劣化,并且内布线图案有大面积可用。
根据本发明的半导体封装方法包括如下步骤:
准备印刷布线板;
准备多个凸起端子,和
将凸起端子安装在印刷布线板的背面的环形连接焊盘上。
根据这种制造方法,由于凸起端子的尺寸是使得仅仅导电涂层的边缘暴露于安装在印刷布线板的背面上的绝缘芯部的平坦面周围,因此背面布线图案也能形成于用于绝缘芯部平坦面的接触区域中。
优选地,准备凸起端子的步骤包括以下步骤:
准备在主表面中形成有多个凹陷部的模具;
将导电涂层淀积在凹陷部的内表面上;和
此后,用绝缘材料填充凹陷部。这种方法用来有效地制造多个凸起端子。
优选地,准备凸起端子的步骤包括以下步骤:
准备绝缘棒;
将导电涂层淀积在绝缘棒的侧面上;此后,
切割所述绝缘棒。这样,就能有效地制造多个凸起端子。
附图说明
图1是根据本发明一个实施例的半导体封装的整体结构的侧视图;
图2是图1中多层印刷布线板和凸起端子的放大横截视图;
图3是图1和2中凸起端子的透视图;
图4是将要接合至图3中凸起端子的背面布线图案的平面图;
图5是示出根据该实施例的多层印刷布线板的变型的视图;
图6是将要接合至图5中凸起端子的背面布线图案的平面图;
图7A是示出根据该实施例的多层印刷布线板的另一变型的视图;
图7B是示出根据该实施例的多层印刷布线板的又一变型的视图;
图8是示出将要接合至根据该实施例的凸起端子的背面线路板的变型的视图;
图9是示出根据该实施例的凸起端子的变型的视图;
图10是示出根据该实施例的凸起端子的另一变型的视图;
图11是用于制造图1所示半导体封装的方法中的凸起端子型模的透视图;
图12是图11所示凸起端子型模的横截视图;
图13是用于利用无电电镀来在图10和12中的凸起端子型模上淀积铜涂层的工序的横截视图;
图14是在图13所示工序之后用来利用电解电镀形成铜涂层的工序的横截视图;
图15是在图14所示工序之后执行的树脂填充工序的横截视图;
图16是在图15所示工序之后用来移除铜涂层的工序的横截视图;
图17A是将要用于在图16所示工序之后施加焊膏工序的掩模的平面图;
图17B是施加焊膏工序的横截视图;
图18A是用于制造图1所示半导体封装的方法中的多层印刷布线板的仰视图;
图18B是沿着线X-X截取的横截视图;
图19是在图17B所示工序之后用来接合凸起端子的工序的横截视图;
图20是在图19所示工序之后用来移除凸起端子型模的工序的横截视图;
图21是用于根据本发明另一实施例的半导体制造方法的绝缘棒的透视图;
图22是用来在图21所示绝缘棒上形成铜涂层的工序的透视图;
图23是在图22所示工序之后用来切掉绝缘棒两端的工序的透视图;
图24是在图23所示工序之后将绝缘棒切割成多段的透视图;
图25A是多层印刷布线板的仰视图;
图25B是沿着图25A中线Y-Y截取的横截视图;
图26A是将要用于将焊膏施加于图25所示多层印刷电路板的工序中的掩模的平面图;
图26B是图26A所示焊膏施加工序的横截视图;
图27是用来定位图24所示凸起端子的定位夹具的透视图;
图28是用来在图26B所示工序之后将定位夹具安装在多层印刷布线板上的工序的横截视图;
图29是用来在图28所示工序之后将凸起端子安装在定位夹具的通孔中的工序的横截视图;
图30是用来在图29所示工序之后用来移除定位夹具的工序的横截视图;
图31A是将要用于将焊膏施加于母板上、以便将在图21至30所示工序期间制造出的半导体封装安装在母板上的工序的掩模的平面图;
图31B是图31A所示焊膏施加工序的横截视图;
图32是用来在图31所示工序之后将半导体封装接合至母板的工序的横截视图;
图33是在图32所示工序之后底填的填充工序的横截视图;和
图34是用于常规半导体封装的多层印刷布线板和凸起端子的结构的横截视图。
[附图标记说明]
10:半导体封装
12:多层印刷布线板
14:IC芯片
16,60,66,94:凸起端子
20:绝缘板
22:正面布线图案
23,24,26,28,30:内布线图案
32:背面布线图案
34:隙孔
36,38:通路
40:平坦面
42,62,96:绝缘芯部
44,64,68,98:导电涂层
45:端面
50,56,58:通路连接盘(via land)
52:连接焊盘
70:凸起端子型模
72:凹陷部
74,76,92:铜涂层
78:树脂
90:绝缘棒
106:定位夹具
108:通孔
具体实施方式
现在将参照附图详细地描述本发明的优选实施例。同一附图标记提供来标识相应或相同的部件,并且对其的描述不重复进行。
参照图1,根据一个实施例的半导体封装10包括其正面上安装有IC芯片14的多层印刷布线板12。半导体芯片10具有BGA结构,并且包括布置在多层印刷布线板12的背面上的栅形阵列的凸起端子16。IC芯片14具有倒装芯片连接结构和栅形阵列的球电极18,在该球电极处IC芯片14焊接到多层印刷布线板12的正面布线图案。
现在参照图2,多层印刷布线板12包括绝缘板20、形成于绝缘板20的正面上的正面布线图案22、嵌入在绝缘板20中的内布线图案23,24,26,28和30、以及形成于绝缘板20背面上的背面布线图案32。正面布线图案22电连接至IC芯片14,并且背面布线图案32电连接至凸起端子16。隙孔34形成于内布线图案28和30中。
多层印刷布线板12还包括嵌入在绝缘板20中的小直径通路36和大直径通路38。容纳在隙孔34中的小直径通路36接触大直径通路38的连接盘39以及通路连接盘50并将它们电连接。
参照图3,每个凸起端子16包括绝缘芯部42和导电涂层44。绝缘芯部42由比如树脂之类的绝缘材料形成,并且具有接合至多层印刷布线板12背面的平坦面40。导电涂层44是比如铜之类的导电材料,其淀积在凸起端子16除了绝缘芯部42的平坦面40之外的所有外表面。凸起端子16具有圆柱体46和半球形头48,并且导电涂层44的端面45显示为与绝缘芯部42的平坦面40处于同一平面上的环。
如图4所示,背面布线图案32包括通路连接盘50、环形连接焊盘52以及将通路连接盘50和连接焊盘52连接起来的引线54。通路连接盘50形成于中心,与绝缘芯部42的平坦面40相对,而环形连接焊盘52形成于外边缘周围,与导电涂层44的环形端面45相对,并且具有稍大于端面45的宽度。那么,由于小直径通路36和大直径通路38紧邻地位于通路连接盘50之上,直径小于平坦面40的隙孔34就也紧邻地位于通路连接盘50之上。
依照本实施例的半导体封装10,各个凸起端子16形成有绝缘芯部42和导电涂层44,并且由于导电涂层44的端面45显示为位于绝缘芯部42的平坦面40周围的环且接合至多层印刷布线板的背面,于是,连接焊盘52也能是环形的。而且,由于通路连接盘50能位于环形连接焊盘52的内侧,通路36和38能紧邻地位于凸起端子16之上,如同通常情况那样。此外,即使隙孔34稍大于通路36的直径,即比连接焊盘52的直径小得多,连接焊盘52与内布线图案28和30之间的寄生电容也不会变得和BGA焊盘为圆形的通常情况那样大。因而,就能防止高频特性的劣化,并且能获得大面积的内布线图案28和30。
在上述实施例中,小直径通路36和大直径通路38紧邻地位于凸起端子16之上。然而,如同图5所示的例子,这些通路也可以位于凸起端子16的边缘处。在此情况下,隙孔34也相对于凸起端子16的边缘对齐。而且,如图6所示,小直径通路36的通路连接盘56能布置在环形连接焊盘52上。或者如图7A所示,仅是小直径通路36可位于凸起端子16的边缘处。如图7B还示出的,对于各个层,可以移动小直径通路36。在这些情况下,内布线图案28和30从上面覆盖凸起端子16,并且连接焊盘52与内布线图案28和30之间的寄生电容仅有很小的增大。
另外,如图8所示,小直径通路36的通路连接盘58可布置为使得它们接触环形连接焊盘52的内侧。
如图9或10所示,可以采用圆柱形凸起端子60或66。图9中的凸起端子60包括圆柱形绝缘芯部62和淀积在圆柱形侧面上的导电涂层64。图10中的凸起端子66的导电涂层68也淀积在绝缘芯部62的底部上。
现在将解释制造半导体封装10的方法。
首先,如图11和12所示,准备树脂、凸起端子型模70。凸起端子型模70具有多个在主表面上布置为栅格的凹陷部72。凹陷部72的位置与要制造的半导体封装10的凸起端子16的位置相一致。每个凹陷部72包括圆柱形侧壁和半球形底部。
如图13所示,利用无电电镀来将薄的铜涂层74淀积于凸起端子模型70的整个表面和淀积在凹陷部72的内壁上。而且,如图14所示,利用电解电镀来用铜涂层76涂覆铜涂层74。
在已经淀积铜涂层74和76之后,用化学物质,比如亚氯酸钠碱溶液,使铜涂层76的表面粗糙化,并且然后,如图15所示,用液体树脂78填充凹陷部72。液体树脂78可以是环氧或丙烯酸紫外固化树脂,例如或者是聚酰亚胺热固树脂。而且,利用刮浆板通过将溢出凹陷部72的树脂移除来将树脂78的上表面弄平。此后,通过紫外辐射或加热来使树脂78固化。
然后,如图16所示,利用比如过硫酸钠溶液之类的化学物质来蚀刻凸起端子型模70的主表面上的多余铜涂层74和76。这样,就将树脂部分78准备为用作绝缘芯部42,并且铜涂层部分74和76用作导电涂层44,而且获得了由绝缘芯部42和导电涂层44组成的凸起端子16。
此后,如图17所示,利用掩模80在暴露于凸起端子型模70的主表面上的导电涂层44的端面上印刷焊膏84。掩模80具有形成为与导电涂层44的环形端面相对应的近似环形切口82。在这个特定过程期间,掩模80覆盖凸起端子型模70并且将切口82与导电涂层44的端面45对齐,将焊膏84施加到导电涂层44的端面45的暴露部分上。然后,在加热所得到的结构以进行回流焊接时,焊膏84沿着导电涂层44的端面45扩展并将其覆盖。
而且,如图18所示,准备多层印刷布线板12,其中背面上暴露了环形连接焊盘52。首先,将阻焊剂86施加于多层印刷布线板12除了连接焊盘52之外的全部背面,并且然后,将焊膏88施加于连接焊盘52。
接着,如图19所示,将在图17所示工序中获得的凸起端子型模70(包括凸起端子16)的主表面与在图18所示工序中获得的多层印刷布线板12的背面对齐,以使得环形导电涂层44的端面与环形连接焊盘52对齐。
在凸起端子型模70与多层印刷布线板12对齐时,加热焊膏84和88一个预定时间以回流焊接。焊膏84和88首先熔化并且然后凝固,凸起端子16就紧紧地安装在多层印刷布线板12的背面上。为了增大接合强度,可将胶粘剂施加于绝缘芯部42的平坦面40,或者连接焊盘52的内侧。
在回流焊接期间熔化的焊膏84和88已经凝固之后,如图20所示,移除凸起端子型模70,完成工艺,由此多个凸起端子16就同时附接到多层印刷布线板12的背面。
根据本实施例的制造方法,能有效地制造出包括凸起端子16的半导体封装10。
现在将描述另一种制造方法。
首先,如图21所示,准备圆柱形树脂绝缘棒90。然后,如图22所示,利用无电电镀和电解电镀来顺序地将铜涂层92淀积在绝缘棒90的所有外表面(侧壁、上表面和底面)上。此后,如图23所示,切掉覆盖端部的铜涂层92,暴露出绝缘棒90的端部,以使得仅侧壁由铜涂层92所覆盖。接着,如图24所示,将其上淀积有铜涂层92的绝缘棒90分割成多段。这样获得的绝缘棒90的分段用作绝缘芯部96,并且淀积在分段上的铜涂层92用作导电涂层98以提供具有预定高度的凸起端子94。
而且,如图25A和25B所示,准备多层印刷布线板12,其背面(图25B中的上表面)上暴露了环形连接焊盘52。
然后,如图26A和26B所示,利用掩模100来将焊膏104印刷在多层印刷布线板12的背面上的环形连接焊盘52的暴露部分上。掩模100包括形成为与环形连接焊盘52相对应的近似环形切口102。具体地,在这个步骤,掩模100被定位为覆盖多层印刷布线板12并且将切口102与连接焊盘52对齐,以使得焊膏104能被施加到连接焊盘52的暴露部分。此后,然而,在回流焊接期间加热所得到的结构时,焊膏104扩展,完全覆盖连接焊盘52。
而且,如图27所示,准备用于定位凸起端子94的夹具106。定位夹具106是矩形板,其厚度约等于凸起端子94的高度,其中形成有包括多个圆形通孔108的栅格。通孔与多层印刷布线板12的连接焊盘52对齐并且相比而言具有稍大的直径。
在已经施加焊膏104之后,如图28所示,将定位夹具106安装在多层印刷布线板12的背面上,并且将通孔108与连接焊盘52对齐。此后,如图29所示,将凸起端子94装配入定位夹具106的通孔108。通过这种工序,能在绝缘棒90的切割表面朝向多层印刷布线板12的背面的情况下安装凸起端子94。仅有一个凸起端子94能安装入每个通孔108。
在已经安装凸起端子94之后,如图30所示,利用回流焊接来加热焊膏104一段预定时期。由于焊膏104首先熔化并且随后凝固,凸起端子94就被紧固到连接焊盘52。在焊膏104已经凝固之后,移除定位夹具106。
根据上述制造方法,能有效地制造出包括凸起端子94的半导体封装。
现在将给出对用来将这样获得的半导体封装安装在母板上的方法的解释。
首先,如图31A和31B所示,使用掩模110并且将焊膏118印刷在形成于母板114上的环形连接焊盘16上。在掩模110中,形成与环形连接焊盘116相对应的近似环形切口112。具体地,在这个步骤,掩模110定位为覆盖母板114并将切口112与连接焊盘116对齐,然后将焊膏118施加于连接焊盘116的暴露部分。此后,在回流焊接期间加热所得到的结构时,焊膏118扩展直到其覆盖所有的连接焊盘116。
在已经施加焊膏118之后,如图32所示,将通过图30所示工序获得的半导体封装与通过图31A和31B所示工序获得的母板对齐,并且凸起端子94面朝下且与连接焊盘116对齐。此后,利用回流焊接将凸起端子94接合至连接焊盘116。多层印刷布线板12和母板114之间的缝隙能通过改变凸起端子94的高度自由地调节。
最后,如图33所示,利用底填材料120来填充多层印刷布线板12和母板114之间的缝隙,并且固化以提供可靠的连接。
根据这种制造方法,将其上已淀积有铜涂层92的单根绝缘棒90分割成多段以提供多个凸起端子94。然而,还可再切割每个短绝缘棒以提供两个凸起端子94。而且,绝缘棒的两端无需被切掉,并且简而言之,切割面只需接合至连接焊盘52。
而且,利用上述任一制造方法,可以在安装IC芯片14之前或之后执行凸起端子16或94的接合。另外,代替制造上述的凸起端子,包括球形、焊板树脂芯部的市售焊球(例如Sekisui Chemical Co.,Ltd.的Micropearl SOL(商标))可切割成两半以用作凸起端子。而且,凸起端子16或94不仅可为圆柱形,还可以替代地为棱柱形,并且简而言之,只要适当地执行其功能,不限于具体形状。最后,所用IC芯片并不限于倒装芯片,并且IC芯片和印刷布线板可通过引线接合而连接。
虽然已经描述了本发明的实施例,然而该实施例仅是实施本发明的一个例子。本发明并不限于以上实施例,而是该实施例可以在不偏离本发明主题的前提下进行各种修改。
Claims (10)
1.一种半导体封装,包括:
印刷布线板;
安装在所述印刷布线板的正面上的集成电路芯片;
多个安装在所述印刷布线板的背面上的凸起端子;
其中每个所述凸起端子包括:
绝缘芯部,其具有朝向所述印刷布线板背面的平坦面;和
导电涂层,其形成于所述凸起端子除了所述绝缘芯部的平坦面之外的外表面上,并且接合至所述印刷布线板的背面的环形连接焊盘上。
2.根据权利要求1的半导体封装,其中所述印刷布线板包括:
绝缘板;
形成于所述绝缘板的正面上并且电连接至所述集成电路芯片的正面布线图案;
嵌入在所述绝缘板中并制造有隙孔的内布线图案;
形成于所述绝缘板的背面上并且电连接至所述凸起端子的背面布线图案,该背面布线图案包括所述环形连接焊盘;和
位于所述隙孔中并电连接至所述背面布线图案的通路。
3.根据权利要求2的半导体封装,其中所述背面布线图案包括:
通路连接盘,设在预定位置,与所述绝缘芯部的平坦面相对,并且电连接至所述环形连接焊盘,和
其中所述通路和所述隙孔布置在所述通路连接盘上。
4.根据权利要求3的半导体封装,其中所述隙孔的直径小于所述绝缘芯部的平坦面的直径。
5.一种半导体封装制造方法,所述半导体封装包括印刷布线板和安装在所述印刷布线板的正面上的集成电路芯片,该制造方法包括:
准备所述印刷布线板;
准备多个凸起端子,每个凸起端子包括:绝缘芯部,其具有朝向所述印刷布线板的背面的平坦面;和导电涂层,其形成于所述凸起端子除了所述绝缘芯部的平坦面之外的外表面上;和
将所述凸起端子安装在所述印刷布线板的背面的环形连接焊盘上。
6.根据权利要求5的半导体封装制造方法,其中所述准备所述凸起端子的步骤包括以下步骤:
准备在主表面中形成有多个凹陷部的模具;
将导电涂层淀积在所述凹陷部的内表面上;和
此后,用绝缘材料填充所述凹陷部。
7.根据权利要求6的半导体封装制造方法,其中所述安装所述凸起端子的步骤包括以下步骤:
至少将焊膏施加于所述印刷布线板的背面的环形连接焊盘上或所述导电涂层与所述绝缘芯部的平坦面处于同一平面上的端面;
此后,将模具与所述印刷布线板对齐以使得模具的主表面朝向所述印刷布线板的背面;
随后加热焊膏一段预定时期;和
在由于加热而熔化的焊膏已经凝固之后,移除模具。
8.根据权利要求5的半导体封装制造方法,其中所述准备所述凸起端子的步骤包括以下步骤:
准备绝缘棒;
将导电涂层淀积在所述绝缘棒的侧面上;和
此后,切割所述绝缘棒。
9.根据权利要求8的半导体封装制造方法,其中所述安装所述凸起端子的步骤包括以下步骤:
至少将焊膏施加于所述印刷布线板的背面的环形连接焊盘上或所述导电涂层与所述绝缘棒的切割面处于同一平面上的端面;
此后,将所述凸起端子安装在所述印刷布线板的背面上以使得绝缘棒的背面朝向所述印刷布线板的背面;和
随后加热焊膏一段预定时期。
10.根据权利要求9的半导体封装制造方法,还包括步骤:
准备具有多个通孔的夹具,
其中所述安装所述凸起端子的步骤包括以下步骤:
将夹具安装在所述印刷布线板的背面上,和
将所述凸起端子装配入通孔,和
其中还包括步骤:在通过加热而熔化的焊膏已经凝固之后移除夹具。
Applications Claiming Priority (2)
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JP2005378948 | 2005-12-28 | ||
JP2005378948A JP4183199B2 (ja) | 2005-12-28 | 2005-12-28 | 半導体パッケージ及びその製造方法 |
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CN1992250A CN1992250A (zh) | 2007-07-04 |
CN100444372C true CN100444372C (zh) | 2008-12-17 |
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US (2) | US7484293B2 (zh) |
JP (1) | JP4183199B2 (zh) |
CN (1) | CN100444372C (zh) |
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JP5050655B2 (ja) | 2006-06-01 | 2012-10-17 | 富士通株式会社 | ビルドアップ基板、それを有する電子部品及び電子機器 |
US20080142964A1 (en) * | 2006-12-13 | 2008-06-19 | Haixiao Sun | Tubular-shaped bumps for integrated circuit devices and methods of fabrication |
CN101521842B (zh) * | 2008-02-29 | 2013-02-13 | 唐华西 | 扬声器磁路结构 |
US8330256B2 (en) | 2008-11-18 | 2012-12-11 | Seiko Epson Corporation | Semiconductor device having through electrodes, a manufacturing method thereof, and an electronic apparatus |
JP2011138846A (ja) * | 2009-12-27 | 2011-07-14 | Kyocer Slc Technologies Corp | 配線基板 |
CN102163558B (zh) * | 2010-02-23 | 2012-12-19 | 日月光半导体制造股份有限公司 | 芯片封装结构的制造方法 |
TWM397596U (en) * | 2010-03-22 | 2011-02-01 | Mao Bang Electronic Co Ltd | Integrated circuit chip card |
KR20120026813A (ko) * | 2010-09-10 | 2012-03-20 | 삼성전기주식회사 | 도전성 전극 구조물의 형성 방법 및 이를 포함하는 태양 전지의 제조 방법, 그리고 상기 태양 전지의 제조 방법에 의해 제조된 태양 전지 |
US9159687B2 (en) * | 2012-07-31 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder bump for ball grid array |
CN106098672A (zh) * | 2016-06-20 | 2016-11-09 | 东莞市联洲知识产权运营管理有限公司 | 一种改进的集成电路封装 |
KR101999594B1 (ko) * | 2018-02-23 | 2019-10-01 | 해성디에스 주식회사 | 반도체 패키지 기판 제조방법, 이를 이용하여 제조된 반도체 패키지 기판, 반도체 패키지 제조방법 및 이를 이용하여 제조된 반도체 패키지 |
WO2021131080A1 (ja) * | 2019-12-27 | 2021-07-01 | ボンドテック株式会社 | 接合方法、被接合物および接合装置 |
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US20070145551A1 (en) | 2007-06-28 |
JP2007180384A (ja) | 2007-07-12 |
US7484293B2 (en) | 2009-02-03 |
CN1992250A (zh) | 2007-07-04 |
JP4183199B2 (ja) | 2008-11-19 |
US20090047755A1 (en) | 2009-02-19 |
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