CN100444335C - 制造包含分离层的多层结构的方法 - Google Patents

制造包含分离层的多层结构的方法 Download PDF

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Publication number
CN100444335C
CN100444335C CNB2005800218458A CN200580021845A CN100444335C CN 100444335 C CN100444335 C CN 100444335C CN B2005800218458 A CNB2005800218458 A CN B2005800218458A CN 200580021845 A CN200580021845 A CN 200580021845A CN 100444335 C CN100444335 C CN 100444335C
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CN
China
Prior art keywords
intermediate layer
layer
power flux
luminous power
impurity
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Expired - Lifetime
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CNB2005800218458A
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Chinese (zh)
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CN1998071A (zh
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米歇尔·布吕埃尔
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Apulinuofu
Soitec SA
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Individual
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)
CNB2005800218458A 2004-06-01 2005-05-20 制造包含分离层的多层结构的方法 Expired - Lifetime CN100444335C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0405883 2004-06-01
FR0405883A FR2870988B1 (fr) 2004-06-01 2004-06-01 Procede de realisation d'une structure multi-couches comportant, en profondeur, une couche de separation

Publications (2)

Publication Number Publication Date
CN1998071A CN1998071A (zh) 2007-07-11
CN100444335C true CN100444335C (zh) 2008-12-17

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CNB2005800218458A Expired - Lifetime CN100444335C (zh) 2004-06-01 2005-05-20 制造包含分离层的多层结构的方法

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US (1) US7846816B2 (https=)
EP (1) EP1774579B1 (https=)
JP (1) JP5335237B2 (https=)
CN (1) CN100444335C (https=)
AU (1) AU2005256723B8 (https=)
BR (1) BRPI0511207A (https=)
FR (1) FR2870988B1 (https=)
WO (1) WO2006000669A2 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8288684B2 (en) * 2007-05-03 2012-10-16 Electro Scientific Industries, Inc. Laser micro-machining system with post-scan lens deflection
FR2961719B1 (fr) 2010-06-24 2013-09-27 Soitec Silicon On Insulator Procede de traitement d'une piece en un materiau compose
FR2965396B1 (fr) * 2010-09-29 2013-02-22 S O I Tec Silicon On Insulator Tech Substrat démontable, procédés de fabrication et de démontage d'un tel substrat
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur
FR2980279B1 (fr) * 2011-09-20 2013-10-11 Soitec Silicon On Insulator Procede de fabrication d'une structure composite a separer par exfoliation
HK1204142A1 (en) * 2012-03-30 2015-11-06 帝人株式会社 Semiconductor laminate and method for manufacturing same, method for manufacturing semiconductor device, semiconductor device, dopant composition, dopant injection layer, and method for forming doped layer
FR2991499A1 (fr) * 2012-05-31 2013-12-06 Commissariat Energie Atomique Procede et systeme d'obtention d'une tranche semi-conductrice
CN106340439A (zh) * 2015-07-06 2017-01-18 勤友光电股份有限公司 用于镭射剥离处理的晶圆结构
DE102016000051A1 (de) 2016-01-05 2017-07-06 Siltectra Gmbh Verfahren und Vorrichtung zum planaren Erzeugen von Modifikationen in Festkörpern
US11130200B2 (en) 2016-03-22 2021-09-28 Siltectra Gmbh Combined laser treatment of a solid body to be split
US10978311B2 (en) 2016-12-12 2021-04-13 Siltectra Gmbh Method for thinning solid body layers provided with components
TWI631022B (zh) * 2016-12-26 2018-08-01 謙華科技股份有限公司 熱印頭模組之製造方法
FR3079657B1 (fr) 2018-03-29 2024-03-15 Soitec Silicon On Insulator Structure composite demontable par application d'un flux lumineux, et procede de separation d'une telle structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030170990A1 (en) * 1998-05-15 2003-09-11 Kiyofumi Sakaguchi Process for manufacturing a semiconductor substrate as well as a semiconductor thin film, and multilayer structure

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2506344B2 (fr) * 1980-02-01 1986-07-11 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
US4415373A (en) * 1981-11-17 1983-11-15 Allied Corporation Laser process for gettering defects in semiconductor devices
KR100481994B1 (ko) * 1996-08-27 2005-12-01 세이코 엡슨 가부시키가이샤 박리방법,박막디바이스의전사방법,및그것을이용하여제조되는박막디바이스,박막집적회로장치및액정표시장치
JP2004140380A (ja) * 1996-08-27 2004-05-13 Seiko Epson Corp 薄膜デバイスの転写方法、及びデバイスの製造方法
JPH1126733A (ja) 1997-07-03 1999-01-29 Seiko Epson Corp 薄膜デバイスの転写方法、薄膜デバイス、薄膜集積回路装置,アクティブマトリクス基板、液晶表示装置および電子機器
US6306729B1 (en) * 1997-12-26 2001-10-23 Canon Kabushiki Kaisha Semiconductor article and method of manufacturing the same
JP3911929B2 (ja) * 1999-10-25 2007-05-09 セイコーエプソン株式会社 液晶表示装置の製造方法
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
US7211214B2 (en) * 2000-07-18 2007-05-01 Princeton University Laser assisted direct imprint lithography
WO2003046967A2 (en) * 2001-11-30 2003-06-05 Koninklijke Philips Electronics N.V. Method of forming a doped region in a semiconductor body comprising a step of amorphization by irradiation
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
US7105425B1 (en) * 2002-05-16 2006-09-12 Advanced Micro Devices, Inc. Single electron devices formed by laser thermal annealing

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030170990A1 (en) * 1998-05-15 2003-09-11 Kiyofumi Sakaguchi Process for manufacturing a semiconductor substrate as well as a semiconductor thin film, and multilayer structure

Also Published As

Publication number Publication date
FR2870988A1 (fr) 2005-12-02
AU2005256723B8 (en) 2011-07-28
FR2870988B1 (fr) 2006-08-11
EP1774579B1 (fr) 2012-05-16
US7846816B2 (en) 2010-12-07
AU2005256723B2 (en) 2011-02-10
BRPI0511207A (pt) 2007-11-27
US20090053877A1 (en) 2009-02-26
JP2008501228A (ja) 2008-01-17
AU2005256723A1 (en) 2006-01-05
CN1998071A (zh) 2007-07-11
EP1774579A2 (fr) 2007-04-18
WO2006000669A3 (fr) 2007-01-25
JP5335237B2 (ja) 2013-11-06
WO2006000669A2 (fr) 2006-01-05

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