CN100440464C - 层叠型半导体器件以及层叠型电子部件的制造方法 - Google Patents

层叠型半导体器件以及层叠型电子部件的制造方法 Download PDF

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Publication number
CN100440464C
CN100440464C CNB2006100584978A CN200610058497A CN100440464C CN 100440464 C CN100440464 C CN 100440464C CN B2006100584978 A CNB2006100584978 A CN B2006100584978A CN 200610058497 A CN200610058497 A CN 200610058497A CN 100440464 C CN100440464 C CN 100440464C
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CN
China
Prior art keywords
mentioned
semiconductor element
equal
film
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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CNB2006100584978A
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English (en)
Chinese (zh)
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CN1841688A (zh
Inventor
芳村淳
大久保忠宣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japanese Businessman Panjaya Co ltd
Kioxia Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1841688A publication Critical patent/CN1841688A/zh
Application granted granted Critical
Publication of CN100440464C publication Critical patent/CN100440464C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Die Bonding (AREA)
CNB2006100584978A 2005-03-28 2006-03-28 层叠型半导体器件以及层叠型电子部件的制造方法 Expired - Lifetime CN100440464C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP092595/2005 2005-03-28
JP092596/2005 2005-03-28
JP2005092595A JP4612450B2 (ja) 2005-03-28 2005-03-28 積層型半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN1841688A CN1841688A (zh) 2006-10-04
CN100440464C true CN100440464C (zh) 2008-12-03

Family

ID=37030623

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100584978A Expired - Lifetime CN100440464C (zh) 2005-03-28 2006-03-28 层叠型半导体器件以及层叠型电子部件的制造方法

Country Status (2)

Country Link
JP (1) JP4612450B2 (https=)
CN (1) CN100440464C (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5680330B2 (ja) * 2010-04-23 2015-03-04 株式会社東芝 半導体装置の製造方法
TWI393494B (zh) 2010-06-11 2013-04-11 欣興電子股份有限公司 具有線路的基板條及其製造方法
CN102315202B (zh) * 2010-07-02 2016-03-09 欣兴电子股份有限公司 具有线路的基板条及其制造方法
JP5384443B2 (ja) * 2010-07-28 2014-01-08 日東電工株式会社 フリップチップ型半導体裏面用フィルム、ダイシングテープ一体型半導体裏面用フィルム、半導体装置の製造方法、及び、フリップチップ型半導体装置
JP2013098240A (ja) * 2011-10-28 2013-05-20 Toshiba Corp 記憶装置、半導体装置及び半導体装置の製造方法
JP6220706B2 (ja) * 2014-03-14 2017-10-25 リンテック株式会社 シート貼付装置および貼付方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288455A (ja) * 1995-04-11 1996-11-01 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002222913A (ja) * 2001-01-24 2002-08-09 Sharp Corp 半導体装置およびその製造方法
JP2004072009A (ja) * 2002-08-09 2004-03-04 Fujitsu Ltd 半導体装置及びその製造方法
JP2004193363A (ja) * 2002-12-11 2004-07-08 Fujitsu Ltd 半導体装置及びその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003041209A (ja) * 2001-07-30 2003-02-13 Hitachi Chem Co Ltd 接着シートならびに半導体装置およびその製造方法
JP3966808B2 (ja) * 2002-12-03 2007-08-29 古河電気工業株式会社 粘接着テープ
JP4316253B2 (ja) * 2003-02-18 2009-08-19 リンテック株式会社 ウエハダイシング・接着用シートおよび半導体装置の製造方法
JP2005327789A (ja) * 2004-05-12 2005-11-24 Sharp Corp ダイシング・ダイボンド兼用粘接着シートおよびこれを用いた半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288455A (ja) * 1995-04-11 1996-11-01 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002222913A (ja) * 2001-01-24 2002-08-09 Sharp Corp 半導体装置およびその製造方法
JP2004072009A (ja) * 2002-08-09 2004-03-04 Fujitsu Ltd 半導体装置及びその製造方法
JP2004193363A (ja) * 2002-12-11 2004-07-08 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP4612450B2 (ja) 2011-01-12
CN1841688A (zh) 2006-10-04
JP2006278519A (ja) 2006-10-12

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TR01 Transfer of patent right

Effective date of registration: 20170807

Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Patentee before: Toshiba Corp.

TR01 Transfer of patent right
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Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Patentee before: Japanese businessman Panjaya Co.,Ltd.

Address after: Tokyo, Japan

Patentee after: Kaixia Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: TOSHIBA MEMORY Corp.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20220107

Address after: Tokyo, Japan

Patentee after: Japanese businessman Panjaya Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: TOSHIBA MEMORY Corp.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20081203