CN100438719C - 混合集成电路装置及其制造方法 - Google Patents
混合集成电路装置及其制造方法 Download PDFInfo
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- CN100438719C CN100438719C CNB2004100787009A CN200410078700A CN100438719C CN 100438719 C CN100438719 C CN 100438719C CN B2004100787009 A CNB2004100787009 A CN B2004100787009A CN 200410078700 A CN200410078700 A CN 200410078700A CN 100438719 C CN100438719 C CN 100438719C
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Abstract
一种混合集成电路装置及其制造方法,本发明的主要目的在于提供一种由一片大版的金属衬底通过切割来制造多个电路衬底的混合集成电路装置的制造方法。本发明的混合集成电路装置(1)具有在表面设置绝缘层(11)的电路衬底(10)和在绝缘层(11)上设置的导电图案(12)。在导电图案(12)上电连接电路元件(13)。另外,电路衬底(10)的侧面具有:自电路衬底(10)的表面周边部向斜下方延伸的第一倾斜部(S1);自电路衬底(10)的背面向斜上方延伸的比第一倾斜部(S1)大的第二倾斜部(S3)。
Description
技术领域
本发明涉及一种混合集成电路装置及其制造方法,特别是涉及一种由一片大版的金属衬底制造多个电路衬底的混合集成电路装置及其制造方法。
背景技术
参照图11说明现有的混合集成电路装置的结构。图11(A)是混合集成电路装置6的立体图,图11(B)是图11(A)的X-X’线的剖面图。
参照图11(A)及图11(B),现有的混合集成电路装置6具有如下的结构:矩形衬底60;导电图案62,其形成在设置于衬底60表面的绝缘层61上;电路元件63,其被固定粘接在导电图案62上;金属细线65,其电连接电路元件63和导电图案62;导线64,其和导电图案62电连接。并且,通过由绝缘性树脂或罩件等密封形成于电路衬底60表面的混合集成电路来完成混合集成电路装置6。
其次,参照图12~图14说明制造混合集成电路装置6的制造方法。
参照图12,说明细长地分割大版的金属衬底66A的工序。在同图中,图12(A)是大版的金属衬底66A的平面图。图12(B)是大版的金属衬底66A的剖面图。
参照图12(A)说明细长地分割大版的金属衬底66A的方法。在此,由切割线D4细长地分割大版的金属衬底66A。该分割通过利用剪切力的剪切进行。另外,考虑其后的接合工序等的操作性,细长地分割的金属衬底也可以分割为两个或两个以上。在此,细长地分割的金属衬底被分割为不同长度的两个金属衬底66B。
参照图12(B)说明金属衬底66A的结构。在此,衬底66A是由铝构成的衬底,两面进行氧化铝膜处理。另外,在形成混合集成电路的面上,为进行金属衬底66A和导电图案的绝缘,设置绝缘层61。并且在绝缘层61上,压附形成导电图案62的铜箔68。
参照图13说明在细长地分割的金属衬底66B的表面形成混合集成电路67的工序。在该图中,图13(A)是形成多个混合集成电路67的细长的金属衬底66B的平面图。图13(B)是图13(A)的剖面图。
首先,通过蚀刻压附在绝缘层61上的铜箔68,形成导电图案62。在此,在细长的金属衬底66B上蚀刻导电图案62,形成多个混合集成电路。另外,为保护导电图案62,有时也在导电图案62上施加树脂外敷层。
其次,使用焊锡等焊料将电路元件63固定在导电图案62上的规定位置。电路元件63可全部采用无源元件或有源元件。另外,在安装功率类的元件时,固定在导电图案上的散热片上安装元件。
参照图14,说明将形成多个混合集成电路67的金属衬底66B分割成各个电路衬底60的方法。在表面形成混合集成电路67的各个电路衬底60通过使用冲压机冲切电路衬底60部分,由金属衬底66B分割。在此,冲压机自形成混合集成电路67的面冲切金属衬底66B。由此,在电路衬底60的周边部形成未形成导电图案62和电路元件63的边缘。
由以上的工序各个分离的电路衬底60经由密封混合集成电路67的工序等,完成制品。
但是,如上所述的混合集成电路装置及其制造方法具有如下所示的问题。
由于通过冲压金属衬底66B由金属衬底66B分离电路衬底60,故至少自电路衬底60的周端部2mm以内的部分形成边缘。由此,电路衬底60的周边部形成死角,即使提高混合集成电路67的集成度,装置整体仍形成大型化。
由与上述相同的理由,不能在电路衬底的周边部配置散热片等电路元件63。这成为设计导电图案62时的制约,不能提高混合集成电路的密度。
另外,由于衬底的侧面部垂直地形成,故当树脂密封该衬底时,衬底和密封树脂的粘附力不强。
通过使用冲压机“冲切”由金属衬底66B分离电路衬底60时,由“冲切”引起的冲击,在电路衬底60表面形成的绝缘层61上产生裂纹。
特别是,在电路衬底60的表面形成多层配线时,对应层积的总数,绝缘层变厚。由此,当形成多层配线时,由绝缘层61产生裂纹的问题更明显。
在金属衬底66B的表面形成绝缘层61,由于绝缘层61中高度填充有氧化铝,故非常硬。由此,进行“冲切”的冲压机的刀刃早期磨损。另外,冲压机的刀刃的更换需要熟练工人操作,更换刀刃的时间非常长,生产性低下。另外,该冲切使用的刀刃的价格非常高。另外该刀刃的寿命非常的短,有可能导致装置整体的生产成本升高。
当利用冲压机的“冲切”自金属衬底66B分离电路衬底60时,金属衬底66B的周边部形成材料损失。因此,作为材料的金属衬底66B废弃损失大。
发明内容
本发明是鉴于上述问题点而开发的。本发明的主要目的在于提供使衬底表面的有效面积增大的混合集成电路装置。另外本发明的这样目的还在于提供一种由一片大版的金属衬底通过切割制造多个电路衬底的混合集成电路装置的制造方法。
本发明的混合集成电路装置包括:电路衬底;导电图案,其被设于所述电路衬底的上面;电路元件,其被电连接于所述导电图案上,其中,所述电路衬底的侧面包括:自所述电路衬底表面周边部向斜下方延伸的第一倾斜部;自所述电路衬底下面的周边部向斜上方延伸的第二倾斜部,所述第一倾斜部的宽度比第二倾斜部窄,相对于所述电路衬底的厚度方向,所述第二倾斜部比所述第一倾斜部大,导电图案的一部分形成在距离所述电路衬底终端部2mm以内的区域,所述导电图案、所述电路元件、所述电路衬底的上面、所述第一倾斜部以及所述第二倾斜部由密封树脂包覆。
本发明混合集成电路装置的制造方法包括如下工序:准备绝缘处理表面的衬底的工序;在所述衬底上面形成导电图案的工序;在所述衬底上面呈格子状形成第一槽,在所述衬底下面呈格子状形成在平面方向和厚度方向上都比所述第一槽更大的第二槽的工序;在所述导电图案上电连接电路元件的工序;由形成所述第一槽及所述第二槽的位置将所述衬底分离成电路衬底,使所述导电图案的一部分位于距所述电路衬底终端部2mm以内的区域的工序;由密封树脂所述导电图案、所述电路元件、所述电路衬底的上面、所述第一倾斜部以及所述第二倾斜部的工序。
在本形态的混合集成电路装置中,第二倾斜部比设于电路衬底侧面的第一倾斜部更大地形成。换而言之,第一倾斜部比第二倾斜部小。由此,可通过使第一倾斜部更小,使可形成导电图案的电路衬底的表面面积增大。
在本形态的混合集成电路装置的制造方法中,首先,形成第一槽及第二槽,将混合集成电路装置装入各电路衬底的表面。通过分离成各个电路衬底,可容易地进行电路衬底的分离。另外,由于在该分离时产生的导电性粉尘极少,故可抑制由粉尘导致的电路的短路。
附图说明
图1是本发明的混合集成电路装置的立体图(A),剖面图(B),立体图(C);
图2是本发明的混合集成电路装置的剖面图(A),剖面图(B);
图3是说明本发明的混合集成电路装置制造方法的平面图(A),立体图(B),放大图(C);
图4是说明本发明的混合集成电路装置制造方法的平面图(A),立体图(B),放大图(C);
图5是说明本发明的混合集成电路装置制造方法的立体图(A),剖面图(B);
图6是说明本发明的混合集成电路装置制造方法的剖面图;
图7是说明本发明的混合集成电路装置制造方法的平面图;
图8是说明本发明的混合集成电路装置制造方法的剖面图;
图9是说明本发明的混合集成电路装置制造方法的立体图(A),剖面图(B),剖面图(C);
图10是本发明的混合集成电路装置制造方法的剖面图;
图11是现有的混合集成电路装置的立体图(A),剖面图(B);
图12是现有的混合集成电路装置的平面图(A),剖面图(B);
图13是现有的混合集成电路装置的平面图(A),剖面图(B);
图14是现有的混合集成电路装置的平面图。
具体实施方式
说明混合集成电路装置1的第一实施方式
参照图1说明由绝缘性树脂密封的混合集成电路装置的结构。图1(A)是混合集成电路装置1的立体图,图1(B)是图1(A)X-X’线的剖面图。图1(C)是电路衬底10的立体图。
参照图1(A)及图1(B)说明混合集成电路装置1的结构。
本发明的混合集成电路装置1包括:电路衬底10,其表面设置绝缘层11;导电图案12,其设于绝缘层11上;电路元件13,其被安装在导电图案12上。另外,电路衬底10的侧面由从电路衬底10的表面周边部向斜下方延伸的第一倾斜部S1和从电路衬底10的背面向斜上方延伸的比第一倾斜部S1大的第二倾斜部S3构成。
作为密封树脂的绝缘性树脂16具有密封由设于电路衬底10表面的电路元件13等构成的混合集成电路的作用。绝缘性树脂16可采用由注入模密封的热塑性树脂和由传递模密封的热硬性树脂等。在此,绝缘性树脂16覆盖形成在电路衬底10表面上的电路,另外,还覆盖电路衬底的侧面部。在此,由于电路衬底10的背面自绝缘性树脂露出,故可使从内装的电路元件13产生的热主动地放出外部。另外,包括电路衬底10背面也可以由绝缘性树脂16密封,此时,可提高装置整体的耐湿性。另外在此,电路衬底10被树脂密封,但也可以采用罩件等其它密封方式。
参照图1(B),电路衬底10的侧面具有自电路衬底10的表面周边部以向外侧鼓起的方式,向斜下方延伸的第一倾斜部S1。另外,第二倾斜部S3自电路衬底10的背面周边部以向外侧鼓起的方式向斜上方延伸。另外第一倾斜部S1和第二倾斜部S3也可以介由垂直于电路衬底10的面方向延伸的垂直部S2连续。
本发明的要旨在于第一倾斜部S1比第二倾斜部S3小。具体地,第一倾斜部S1和第二倾斜部S3相对水平方向斜向延伸。由此,这些倾斜部越小,对横向的延伸距离越小。由此,可通过使第二倾斜部S3比第一倾斜部S1大,尽可能地减小第一倾斜部S1,来减小第一倾斜部S1的横向的延伸距离。由此,可尽可能加大电路衬底16的表面的有效面积,可加大可形成导电图案12的面积。
参照图1(C),混合集成电路装置1具有如下的结构。即,混合集成电路装置1包括:由金属构成的电路衬底10;在电路衬底10表面形成的绝缘层11;在绝缘层11上形成的导电图案12;在导电图案12上的规定位置安装的电路元件13等。以下详细说明如上各结构要素。
电路衬底10的材料采用铝、铜、铁等金属。另外,电路衬底10的材料也可以采用这些金属的合金。在此,采用由铝构成的电路衬底10,其两面可以进行氧化铝膜处理。形成电路衬底10的具体的制造方法在后面的“说明混合集成电路装置制造方法的实施方式”中论述。
绝缘层11在电路装置10的表面形成,具有绝缘导电图案12和电路衬底的作用。另外,为使自电路元件13发出的热主动地传给电路衬底10,在绝缘层11内高度填充氧化铝。
导电图案12设置在绝缘层11的表面,由铜等金属形成。在此,在电路衬底10的整个表面形成导电图案12。具体地,导电图案12也形成在距电路衬底10周端2mm以内的周端部附近。这样,可直至电路衬底10周边部附近的表面形成导电图案12的理由在于分割电路衬底10的方法。分割电路衬底10的方法在后面详细论述。在本发明中,通过切断金属衬底来从大版的金属衬底分割各个电路衬底10。在现有例中,由于通过冲压分割电路衬底,故必须在电路衬底10的周端部附近留有边缘,但在本发明中,可消除该边缘。由此,可在电路衬底10的整个表面区域形成导电图案12。更具体地,自电路衬底11的周端部至最外侧导电图案的距离可达到0.5mm左右。
介由焊锡等焊料将电路元件13安装在导电图案12的规定位置。电路元件13可全部采用无源元件、有源元件或电路装置等。另外,当安装功率类的元件时,在固定在导电图案上的散热片上安装该元件。在本发明中,电路元件13可配置在电路衬底10的任意位置。即,在电路衬底10的周端部附近也可以配置电路元件13。在此有源元件采用晶体管、LSI芯片、二极管等。无源元件采用片状电阻、片状电容等。另外,无源元件还采用电感、热敏电阻、天线、振荡器等两端具有电极部的元件。另外,树脂密封型封装件等也可以作为电路元件固定在导电图案13上。
散热片13A被安装在导电图案12的规定位置。然后,在其上面安装功率类半导体元件,并利用金属细线15将功率类元件和导电图案12电连接。在此,散热片13A可配置在电路衬底10的任意位置。具体地,散热片13A也可以配置在距电路衬底10的周端2mm以内的周端部附近。这样,可直至电路衬底10周端部附近的表面配置散热片13A的理由在于分割电路衬底10的方法。
分割电路衬底10的方法在后面详细论述,在本发明中,通过切断金属衬底自大版的金属衬底分割成各个电路衬底10。在现有例中,由于通过冲压分割电路衬底,故电路衬底10的周端部附近必须留有边缘。另外,安装功率类元件的散热片13在电路元件13中的高度最高。由此,不能在电路衬底10的周端部配置。在本发明中,可消除该边缘,可在电路衬底10表面的任意位置配置散热片13A。同样,其它电路元件13也可以这样。
导线14被固定在由导电图案12形成的焊盘上,具有和外部进行输入、输出的作用。另外,在导电图案12上,在不进行电连接的位置也可施加树脂等构成的外敷层。
根据上述的混合集成电路装置10的结构,可达到如下所示的效果。
由于直至电路衬底10的端部附近均可形成导电图案12,故在形成和现有例相同的电路时,可将混合集成电路装置整体的尺寸减小。
由于直至电路衬底10的端部附近均可配置电路元件13,故可提高设计电路的自由度。另外,由于可提高图案的密度,故在形成和现有例相同的电路时,可将混合集成电路装置整体的尺寸减小。
由于在电路衬底10的倾斜部和绝缘性树脂16之间产生锚固效应,故可防止电路衬底10自绝缘性树脂16脱离。
电路衬底10背面和侧面连接的部分形成钝角,不形成带圆角的形状。由此,在使用模型露出电路衬底的背面由绝缘性树脂16进行密封的工序中,可防止绝缘性树脂16侵入模型和电路衬底10之间的缝隙内。由此,可防止绝缘性树脂16附着到电路衬底10的背面。
参照图2(A)的剖面图说明电路衬底10侧面部的结构。首先,将第一倾斜部S1和电路衬底10表面形成的角度设为a1。并且,将第二倾斜部S3和电路衬底10背面形成的角度设为a2。此时,最好减小a1,通过减小该角度a1,可使电路衬底10整体的端部和电路衬底10表面的端部的距离d1更小。由此,可增大电路衬底10表面的实际面积,增大可形成导电图案10的有效面积。
另外,角度a2最好尽可能大。具体地,a2最好比所述的a1大。这是因为在后述的树脂密封工序中可通过将密封树脂填入第二倾斜部S3的里面提高电路衬底10和树脂的附着强度。
另外,当将电路衬底10整体的周端部和电路衬底10背面的周端部的距离设为d2时,该d2比d1大。另外通过将该d2加长,可提高覆盖电路衬底表面及侧面的密封树脂和电路衬底10侧面的附着性。
参照图2(B),在此,在电路衬底10表面形成多层导电图案。具体地,在由金属构成的电路衬底10的表面形成第一绝缘层11A。然后,在第一绝缘层11A的表面上制图形成第一导电图案12A。进一步介由第二绝缘层11B在第一导电图案12A的上方形成第二导电图案12B。贯通第二绝缘层11B在规定的位置电连接第一导电图案12A和第二导电图案12B。另外,电路元件13固定在上层的第二导电图案12B上。在此,说明了两层的配线结构,但也可以形成三层以上的配线结构。
通过形成多层配线结构,绝缘层11也形成多层。由此,随着导电图案13的层数的增加,绝缘层11变厚。具体地,在形成一层导电图案12时,绝缘层11的厚度为60μm左右。与此相对,在形成第一导电图案12A及第二导电图案12B时,将第一绝缘层11A及第二绝缘层12B相加的厚度为120μm左右。在表面形成这样厚的绝缘层11的电路衬底的分离用现有的冲压方法是困难的。这是因为冲压的冲击容易使厚的绝缘层11上发生裂纹。
说明混合集成电路装置制造方法的第二实施方式
参照图3~图10,说明由第一实施方式说明的混合集成电路装置的制造方法。
第一工序:参照图3
本工序通过分割大版的金属衬底10A形成中版的金属衬底10B。
首先,参照图3(A),准备大版的金属衬底10A。例如,大版的衬底10A是边长约1m的正方形。在此,金属衬底10A是两面进行了氧化铝膜处理的铝衬底。然后,在金属衬底10A的表面设置绝缘层。另外,在绝缘层表面形成构成导电图案的铜箔。另外在形成多层导电图案时,介由绝缘层粘附多片铜箔。
其次,参照图3(B),利用切割锯3 1沿切割线D1分割金属衬底10A。在此,将多个金属衬底10A重叠,同时分割多片金属衬底10A。切割锯31高速旋转,同时沿切割线D1分割金属衬底10A。作为分割的方法,在此,通过将具有正方形状的大版的金属衬底10A沿切割线D1分割成8片,形成细长的中版的金属衬底10B。中版的金属衬底10B的形状为长边长度是短边长度两倍的长度。
参照图3(C)说明切割锯3 1的刀刃的形状等。图3(C)是切割锯31的刀刃31A附近的放大图。刀刃31A的端部平坦地形成,并填入金刚石。可通过高速地旋转具有这样刀刃的切割锯,沿切割线D1分割金属衬底10A。
由该工序制造的中版的金属衬底10B,通过蚀刻部分除去铜箔,形成导电图案。形成的导电图案的个数根据金属衬底10B的大小和混合集成电路的大小设定,也可以将形成数十个至数百个混合集成电路的导电图案形成在一片金属衬底10B上。
在此,金属衬底10的分离也可以通过冲切进行。具体地,可以通过冲切形成具有相当于数个(例如2至8个)电路衬底的大小的金属衬底10B。
第二工序:参照图4及图5
本工序在中版的金属衬底10B的表面及背面呈格子状形成第一槽20A及第二槽20B。图4(A)是由前工序分割的中版的金属衬底10B的平面图,图4(B)是表示使用V切割锯35在金属衬底10A上形成槽时的状态的立体图,图4(C)是刀刃35A的放大图。
参照图4(A)及图4(B),使V切割锯35高速旋转,沿切割线D2在金属衬底10B的表面形成第一槽20A。另外,在对应第一槽20A的位置的金属衬底10B的背面形成第二槽20B。切割线D2呈格子状设置。切割线D2与构成在绝缘层11上形成的各电路的导电图案(单元)的边界线相对应。
参照图4(C),说明V切割锯35的形状。在V切割锯35上设置多个具有该图所示形状的刀刃35A。在此,刀刃35A的形状与设置于金属衬底10A上的槽的形状相对应。在此,在金属衬底的两面形成具有V型断面的槽。因此,刀刃35A的形状也形成V型。另外,在刀刃35A内埋有金刚石。
其次,参照图5(A)及图5(B),说明形成了槽20的金属衬底10B的形状。图5(A)是由切割锯31形成槽的金属衬底10B的立体图,图5(B)是金属衬底10B的剖面图。
参照图5(A),在金属衬底10B的表面及背面呈格子状形成第一槽20A及第二槽20B。在此,第一槽20A和第二槽20B的平面位置准确地对应。在本实施例中,由于使用具有V型形状的刀刃35A的V切割锯35形成槽,故槽20形成V型的断面。另外,槽20的中心线与构成在绝缘层11上形成的各电路的导电图案12(单元)的分界线相对应。在此,在形成树脂层11的面上形成第一槽20A,在其相反面上形成第二槽20B。
参照图5(B),说明槽20的形状等。在此,槽20形成大致V型的剖面。第一槽20A及第二槽20B的深度比金属衬底10B的厚度的一半浅。由此,在本工序中,金属衬底10B未被分割成各电路衬底10。即,各电路衬底10由对应槽20的部分的金属衬底10B的残存厚度部分连接。由此,作为各电路衬底10在分割前金属衬底10B可以作为一个片状物处理。另外,在本工序中,当产生毛刺时,通过进行高压清洗去除毛刺。在此,第二槽形成比第一槽10A大。
在此,第一及第二槽20A、20B的宽度和深度可相应调节。具体地,可通过减小第一槽20A开口的角度β1,增大可形成导电图案12的有效面积。另外,即使将第一槽20A的深度变浅,也可以达到同样的效果。可通过将第二槽20B开口的角度β2增大,在后述的工序中,促进向该第二槽20B附近的树脂的填入。在此,第二槽20B比第一槽20A大。
第三工序:参照图6~图7
本工序在导电图案12上安装电路元件13,将电路元件13和导电图案12进行电连接。
参照图6,说明在导电图案12上安装电路元件13的装片工序。介由焊锡等焊料将电路元件13安装在导电图案12的规定位置。如前所述,导电图案12也形成在电路衬底10的周端部附近。由此,电路元件13也可以被安装在电路衬底10的周端部附近。另外,当在上面安装功率类元件的散热片13A和其它电路元件比较时,是具有高度的电路元件。由此,在使用冲压机的现有的混合集成电路装置的制造方法中,不能在电路元件13的周端部附近配置散热片13A。在本发明中,使用圆切割锯将电路元件10各个分离,对此将后述。因此,可将散热片13A等具有高度的电路元件13配置在电路元件13的周端部附近。
其次,说明进行电路元件13和导电图案12的电连接的引线接合工序。在此,对在一片金属衬底10B上形成的数十至数百个的混合集成电路一并进行引线接合。
参照图7具体说明在金属衬底10B上形成的混合集成电路。图7是在金属衬底10B上形成的混合集成电路17的一部分的平面图,实际上形成更多个混合集成电路17。另外,在同图中由虚线表示将金属衬底10B分割成各个电路衬底10的切割线D3。由同图可知,形成各混合集成电路的导电图案12和切割线D2极其接近。由此可知,在金属衬底10B的整个表面形成导电图案12。另外可知,散热片13A等电路元件13被配置在混合集成电路的周边部。
在所述说明中,在具有细长形状的衬底10B的表面一次形成混合集成电路。在此,在进行装片和引线接合的制造装置中存在制约时,也可在本工序的前工序中将金属衬底10B分割成规定的尺寸。例如,在本工序的前工序中,将金属衬底10B分割成两块,金属衬底形成正方形状。
第四工序:参照图8及图9
本工序通过在形成槽20的位置分割金属衬底10B,将各电路衬底10分开。图8是表示通过折曲金属衬底10B分割成电路衬底10的方法的剖面图。另外图9(A)是表示使用圆刀片41将金属衬底10B分割成各电路衬底10的状态的立体图。图9(B)是图9(A)的剖面图。在此,虽未图示,但在图9(A)中,在绝缘层11上形成多个混合集成电路。
参照图8说明通过折曲将金属衬底10B分割成各电路衬底10的方法。在该方法中,局部折曲金属衬底10B,使形成第一槽20A及第二槽20B的位置折曲。形成第一槽20A及第二槽20B的位置仅由未形成槽20的厚度部分连接。由此,可通过在该位置折曲,容易地将各电路衬底10分离。另外,金属衬底10B的局部折曲自背面进行,使在金属衬底10B的表面形成的电路不被破坏。
其次,参照图9,说明利用圆刀片41进行金属衬底10B的分割的方法。参照图9(A),使用圆刀片41沿切割线D3压切金属衬底10B。由此,金属衬底10B被分割成各电路衬底10。圆刀片41压切未形成金属衬底10B的槽20的厚度部分的对应槽20中心线的部分。
参照图9(B)详细说明圆刀片41。圆刀片41具有圆板形状,其周端部形成锐角。圆刀片41的中心部固定在支承部42上,使圆刀片41可自由转动。所述的切割锯利用驱动力高速旋转,同时切断金属衬底10B。在此,圆刀片41没有驱动力。即,通过将圆刀片41的一部分压接在金属衬底10B上,同时沿切割线D3移动来使圆刀片41旋转。另外,参照图9(B),在本发明中,可将散热片13A等具有高度的电路元件13配置在电路衬底10的周边部。由此,如同图所示,散热片13A的位置有时接近电路衬底10的周边部。即使这样,支承部42也不接触散热片13A。因此,可将散热片13A等高的元件配置在电路衬底10的周边部。
另外除上述方法外,使用激光也可以分离各电路衬底10。此时,在设置第一槽20A的位置照射激光。参照图9(C),在此,在电路衬底10的表面形成由第一导电图案12A及第二导电图案12B构成的多层配线。由于形成多层导电图案,使绝缘层11变厚。由此,用冲压机冲切进行的各电路衬底10的分离变得困难。因此,在本实施例中,使用上述圆刀片41进行衬底的分离。由此,可不损伤绝缘层11,将各电路衬底10分离。
第五工序:参照图10
参照图10说明由绝缘性树脂16密封电路衬底10的工序。图10是表示使用模型50由绝缘性树脂16密封电路衬底10的工序的剖面图。
首先,在下模50B上载置电路衬底10。其次,自浇口53注入绝缘性树脂16。密封方法可采用使用热硬性树脂的传递模模制或使用热硬性树脂的注入模。然后,介由排气口54将与自浇口53注入的绝缘性树脂1 6的量对应的模腔内部的气体排出外部。
如上所述,在电路衬底10的侧面部设有倾斜部。由此,通过由绝缘树脂密封将绝缘性树脂16填入倾斜部,由此,在绝缘性树脂16和倾斜部之间产生锚固效应,将绝缘性树脂16和电路衬底10的接合强化。另外,可使耐湿性提高。
通过所述的工序,由树脂进行密封的电路衬底10经由引线切割工序等作为制品完成。
通过本实施方式,可达到如下所述的效果。
由于在金属衬底10B的表面及背面呈格子状形成第一槽20A及第二槽20B,故可容易地在形成槽的位置分割电路衬底10。该各电路衬底10的分割可考虑通过折曲进行分割和通过圆刀片41进行分割这两种方法,其任何一种方法都可以容易地进行分割。
由于使用高速旋转的切割锯31分割大版的金属衬底,故和现有使用剪切的衬底的分割方法比较,毛刺的产生非常少。由此,可防止在制造工序的中途阶段等,由毛刺造成混合集成电路短路,产生不良品。
另外,即使在切割锯31磨损的情况下,切割锯31的更换作业比较简单,可迅速进行。由此,和现有剪切的刀的更换相比,可提高操作效率。
另外,可在一片金属衬底10B上装入数十个至数百个混合集成电路。由此,可集中进行蚀刻工序、装片工序及引线接合工序。由此,可使生产效率提高。
另外,在将金属衬底10B分割成各个电路衬底10的工序中,通过在金属衬底10B上压接没有驱动力的圆刀片41,使其旋转,分割电路衬底10B。因此,由于圆刀片41将槽20的残留厚度部分和绝缘层11切除,故不产生切削屑。由此,在制造工序中,可防止混合集成电路产生短路。
另外,通过在对应槽20的部分压接圆刀片41,进行金属衬底10B的分割。由此,可防止在树脂层11上产生裂纹,防止电路衬底的耐压性降低。另外,可确保衬底10B的平坦性。
另外,即使在圆刀片41磨损的情况下,圆刀片41的更换作业比较简单,可以在短时间内进行。由此,可使生产效率提高。
另外,在本发明中,通过使用切割锯31或圆刀片41“切断”金属衬底,使各电路衬底分离。如现有例,在使用冲压机进行电路衬底的分离时,必须对应制造的电路衬底的大小,准备不同的刀具。在本发明中,即使在制造具有不同大小的电路衬底的混合集成电路装置时,也可以仅通过变更切割线而对应。
另外,在本发明中,在一片金属衬底10B上呈阵列状组装多个混合集成电路。并且,由于各混合集成电路相互之间极其地接近,故金属衬底10B的大致整个面形成电路衬底10。由此,可降低材料的废弃损耗。
另外,由于在金属衬底10B上形成第一槽20A及第二槽20B的V切割锯35的刀刃35A上设置平坦部35B,故可减少刀刃35A的磨损。由此,可防止V切割锯35的切割性能早期降低。另外,即使在设有树脂层11的金属衬底10B的面上形成第一槽20A,也可以防止在树脂层11上产生裂纹。
Claims (8)
1.一种混合集成电路装置,其特征在于,包括:金属材料在侧面露出的电路衬底;导电图案,其设于所述电路衬底的上面;电路元件,其被电连接于所述导电图案上,
所述电路衬底的四个侧面包括:自所述电路衬底上面周边部向斜下方延伸的第一倾斜部;自所述电路衬底下面的周边部向斜上方延伸的第二倾斜部,
所述第一倾斜部的宽度比第二倾斜部窄,相对于所述电路衬底的厚度方向,所述第二倾斜部比所述第一倾斜部大,
导电图案的一部分形成在距离所述电路衬底终端部2mm以内的区域,
所述导电图案、所述电路元件、所述电路衬底的上面、露出所述金属材料的所述第一倾斜部以及所述第二倾斜部由密封树脂包覆。
2.如权利要求1所述的混合集成电路装置,其特征在于,所述导电图案形成多层。
3.如权利要求1所述的混合集成电路装置,其特征在于,在所述电路衬底的上面上形成绝缘层。
4.一种混合集成电路装置的制造方法,其包括如下工序:准备上面绝缘处理的、由金属构成的衬底的工序;在所述衬底上面形成导电图案的工序;在所述衬底上面呈格子状形成第一槽,在所述衬底下面呈格子状形成在平面方向和厚度方向上都比所述第一槽大的第二槽的工序;在所述导电图案上电连接电路元件的工序;在形成所述第一槽及所述第二槽的位置将所述衬底分离成电路衬底,使所述导电图案的一部分位于距所述电路衬底终端部2mm以内的区域,并且在各个所述电路衬底的四个侧面,构成从所述电路衬底的上面的周边部向斜下方延伸的第一倾斜部和从所述电路衬底的下面的周边部向斜上方延伸的第二倾斜部的工序;由密封树脂包覆所述导电图案、所述电路元件、所述电路衬底的上面、露出所述金属材料的所述第一倾斜部以及所述第二倾斜部的工序。
5.如权利要求4所述的混合集成电路装置的制造方法,其特征在于,在将所述衬底分离成所述电路衬底的工序中,通过在所述第一槽压接没有驱动力的圆刀片并使其旋转,进行所述电路衬底的分割。
6.如权利要求4所述的混合集成电路装置的制造方法,其特征在于,在将所述衬底分离成所述电路衬底的工序中,通过在所述第一槽内照射激光,进行所述电路衬底的分割。
7.如权利要求4所述的混合集成电路装置的制造方法,其特征在于,在形成所述第一槽以及所述第二槽的工序中,通过使具有对应所述第一槽或第二槽的断面形状的刀刃的切割锯高速旋转,形成所述第一槽或所述第二槽。
8.如权利要求4所述的混合集成电路装置的制造方法,其特征在于,在将所述衬底分离成所述电路衬底的工序中,在设有所述第一槽及所述第二槽的位置,通过弯曲所述衬底而进行分离,得到独立的所述电路衬底。
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KR (1) | KR100613792B1 (zh) |
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JP2008299712A (ja) * | 2007-06-01 | 2008-12-11 | Nec Electronics Corp | 半導体装置 |
KR101505551B1 (ko) * | 2007-11-30 | 2015-03-25 | 페어차일드코리아반도체 주식회사 | 온도 감지소자가 장착된 반도체 파워 모듈 패키지 및 그제조방법 |
JP5108496B2 (ja) * | 2007-12-26 | 2012-12-26 | 三洋電機株式会社 | 回路基板およびその製造方法、回路装置およびその製造方法 |
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WO2010149762A2 (en) * | 2009-06-25 | 2010-12-29 | Imec | Biocompatible packaging |
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WO2011078349A1 (ja) * | 2009-12-24 | 2011-06-30 | 京セラ株式会社 | 多数個取り配線基板および配線基板ならびに電子装置 |
KR101148226B1 (ko) * | 2010-05-24 | 2012-05-22 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP5278608B2 (ja) * | 2010-05-26 | 2013-09-04 | 株式会社村田製作所 | 部品内蔵基板 |
USD637192S1 (en) * | 2010-10-18 | 2011-05-03 | Apple Inc. | Electronic device |
JP5796956B2 (ja) | 2010-12-24 | 2015-10-21 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置およびその製造方法 |
US8933468B2 (en) | 2012-03-16 | 2015-01-13 | Princeton University Office of Technology and Trademark Licensing | Electronic device with reduced non-device edge area |
US9408301B2 (en) | 2014-11-06 | 2016-08-02 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US11437304B2 (en) | 2014-11-06 | 2022-09-06 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US9397017B2 (en) | 2014-11-06 | 2016-07-19 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
CN108028242B (zh) * | 2015-09-30 | 2021-08-17 | 敏捷电源开关三维集成Apsi3D | 包括附加迹线的半导体功率器件及制造半导体功率器件的方法 |
DE102019129675A1 (de) | 2018-12-11 | 2020-06-18 | Infineon Technologies Ag | Leistungshalbleitermodul und Verfahren zum Herstellen eines Leistungshalbleitermoduls |
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- 2004-09-17 CN CNB2004100787009A patent/CN100438719C/zh not_active Expired - Fee Related
- 2004-09-17 KR KR20040074513A patent/KR100613792B1/ko not_active IP Right Cessation
- 2004-09-20 TW TW93128408A patent/TWI271125B/zh not_active IP Right Cessation
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US20070226996A1 (en) | 2007-10-04 |
CN1602139A (zh) | 2005-03-30 |
KR20050030550A (ko) | 2005-03-30 |
TW200520638A (en) | 2005-06-16 |
KR100613792B1 (ko) | 2006-08-22 |
US20050067186A1 (en) | 2005-03-31 |
US7232957B2 (en) | 2007-06-19 |
TWI271125B (en) | 2007-01-11 |
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