CN100376021C - 适用于集成电路或分立元件的平面凸点式封装工艺 - Google Patents

适用于集成电路或分立元件的平面凸点式封装工艺 Download PDF

Info

Publication number
CN100376021C
CN100376021C CNB2005100412746A CN200510041274A CN100376021C CN 100376021 C CN100376021 C CN 100376021C CN B2005100412746 A CNB2005100412746 A CN B2005100412746A CN 200510041274 A CN200510041274 A CN 200510041274A CN 100376021 C CN100376021 C CN 100376021C
Authority
CN
China
Prior art keywords
metal
pin
chip
plastic
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2005100412746A
Other languages
English (en)
Other versions
CN1738014A (zh
Inventor
王新潮
于燮康
梁志忠
谢洁人
陶玉娟
周正伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changdian Technology Management Co ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CNB2005100412746A priority Critical patent/CN100376021C/zh
Publication of CN1738014A publication Critical patent/CN1738014A/zh
Priority to PCT/CN2006/000610 priority patent/WO2006122467A1/zh
Priority to PCT/CN2006/000607 priority patent/WO2006105733A1/zh
Priority to PCT/CN2006/000609 priority patent/WO2006105735A1/zh
Priority to PCT/CN2006/000608 priority patent/WO2006105734A1/zh
Priority to US11/910,893 priority patent/US20080285251A1/en
Priority to US11/910,885 priority patent/US20080315412A1/en
Priority to US11/910,878 priority patent/US20080258273A1/en
Application granted granted Critical
Publication of CN100376021C publication Critical patent/CN100376021C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种适用于集成电路或分立元件的平面凸点式封装工艺，包括以下工艺步骤：取金属基板(1)，在基板的两面各自贴上干膜层(2、3)，在基板(1)的两面对应去除部分干膜，在基板上准备形成基岛及引脚，在基板上准备形成基岛及引脚区域的两面都镀上活化物质和金属层，去除基板正面余下的干膜，半蚀刻，在基板(1)上形成凹陷的半蚀刻区(1.3)，同进相对形成基岛1.1及引脚1.2，去除基板背面余下的干膜，在基岛正面金属层植入芯片(9)，打金属线(10)，包封塑封体(11)，正面打印(12)，半蚀刻区(1.3)余下部分金属1.4再次进行蚀刻，塑封体正面贴上胶膜(13)，切割。本发明焊性能力强、品质优良、成本较低、生产顺畅、适用性较强、多芯片排列灵活、不会发生塑封料渗透的种种困扰。

Description

适用于集成电路或分立元件的平面凸点式封装工艺
技术领域：
本发明涉及一种适用于集成电路或分立元件的平面凸点式封装工艺。属适用于集成电路或分立元件的封装技术领域。
背景技术：
传统的适用于集成电路或分立元件的超薄无脚封装工艺及其封装结构，其封装型式为四面无脚表面贴片式封装，阵列式集合体经切割成为单一的单元。其基板型式为引线框式。其主要存在以下不足：
1、引线框：采用穿透式蚀刻的方式制作引线框。
2、化学胶膜：因采用穿透式蚀刻方式，在包封过程中会造成溢料。
3、污染：因为采用化学胶带，而在各种高温工艺中胶膜的粘剂很容易因为高温而气化出来，间接污染或覆盖在芯片的压区及打线区的表面，常常造成打线能力的不稳定。
4、金属丝球焊：因采用穿透式蚀刻方式，背面必须贴上防止溢料用的胶膜。而在焊线过程设定的压力参数、振荡参数等会因为胶膜是软性的，会有部分被吸收，所以实际的压力值和振荡值与设定值相比会有出入，从而造成焊线点松脱，严重影响了焊线的可靠性及生产稳定性。
5、可靠性
A.虽然贴了化学胶膜，但在高温包封过程中，还是会有不同程度的溢料；
B.因为担心溢料后产生大量的返工作业，所以不敢用较大的包封压力，结果造成了塑封料疏松、吸水率增加、密度降低，严重增加了生产成本及良率成本；
C.四面表面贴片式封装型式的底部输出脚的部分是与塑封表面呈同高甚至是凹陷的，在表面贴装过程中会因为脚掌共面性不良而产生接触不良的问题；同时，由于外脚凹陷于塑封体的平面，表面贴装作业中会有空气残留于凹陷中，经高温空气膨胀后，会造成接点的崩裂；
D.因输出脚与塑封体是在同一平面甚至是凹陷的，在表面贴装过程中很容易造成凸脚表面锡膏相互连结而短路；
E.打线的内脚原则上采用镀银层，然而银层与塑封料的接合能力并不好，很容易造成塑封料与银层间的脱层的问题；
F.电性输出的外脚原则上采用锡铅、纯锡等材料，而因材料本身容易氧化，所以会影响到可焊性的能力，而且保存的时间也较短。
G.由于电性输出脚的外脚原则上采用锡铅、纯锡等材料，而锡的熔点相对较低，这样在切割工序时很容易因为切割刀的磨擦生热而造成锡的氧化甚至是熔化，进而大大影响了输出脚的可焊性和电性传输稳定性。
6、散热性、导电率：四面表面贴片式封装的引线框均采用全蚀刻的铜合金，其导电率/散热能力仅有65％左右，如果采用纯铜的材料，其导电率/散热能力至少可达99％以上；但因纯铜的强度太软，所以在生产过程中容易产生因引线框太软而易变形的困扰。
发明内容：
本发明的目的在于克服上述不足，提供一种生产顺畅，良率提高，成本低廉，品质优良，可靠性高，导电率/散热性高的适用于集成电路或分立元件的平面凸点式封装工艺。
本发明的目的是这样实现的：一种适用于集成电路或分立元件的平面凸点式封装工艺，包括以下工艺步骤：
——取一片金属基板，
——在金属基板的两面各自贴上干膜层以保护后续的蚀刻工艺作业，
——在金属基板的两面对应去除部分干膜，在金属基板上准备形成基岛及引脚，用意是露出基板上后续需要镀活化物质的区域，
——在金属基板上准备形成的基岛及引脚区域的两面都镀上活化物质；
——在金属基板上准备形成的基岛及引脚区域两面的活化物质上都镀上金属层，以利于后续焊线时金属线与芯片区和打线内脚区之间以更加紧密、牢固的接合，同时增加与塑封料饼间的结合度，
——去除金属基板正面余下的干膜，以露出后续所需半蚀刻工艺的区域，
——对去除了金属基板正面余下的干膜的区域进行半蚀刻，在金属基板上形成凹陷的半蚀刻区，同时相对形成基岛及引脚，
——去除基板背面余下的干膜，
——在金属基板的基岛正面金属层上进行芯片的植入，制成适用于集成电路或分立元件的的阵列式集合体半成品，
——对已完成芯片植入作业的半成品进行打金属线作业，
——将已打线完成的半成品正面进行包封塑封体作业，并依据塑封料的特性进行塑料包封后固化作业，以保护金属线、芯片及内脚的安全，
——将已完成塑料包封及后固化作业的半成品，进行正面打印作业，用以识别芯片的功能及特性，
——在金属基板的背面对不被金属层覆盖的区域即半蚀刻区余下部分的金属再次进行蚀刻，从而使基岛和引脚的背面凸出于塑封体，
——将塑封体正面贴上胶膜，准备进行后续的塑封体切割作业，
——对已贴上胶膜的半成品进行切割作业，使原本以阵列式集合体方式连在一起的芯片一颗颗独立开来，
——将完成切割的产品利用取放转换设备将单颗适用于集成电路或分立元件的的塑封体逐一的吸出胶膜。
本发明适用于集成电路或分立元件的平面凸点式封装工艺，所述的芯片的植入可以在基岛正面金属层上直接进行芯片的植入，也可以先在基岛正面金属层上涂布上银胶，再在刚刚完成银胶涂布的银胶上进行芯片的植入，完成后再进行银胶后固化的作业。
本发明适用于集成电路或分立元件的平面凸点式封装工艺，镀在基岛及引脚上面的所述金属层为金或银、铜、镍、镍钯层。
本发明适用于集成电路或分立元件的平面凸点式封装工艺，镀在基岛及引脚下面的所述金属层为金或银、铜、锡、镍、镍钯层。
本发明适用于集成电路或分立元件的平面凸点式封装工艺，所述的金属线为金线或银线、铜线、铝线。
本发明集成电路或分立元件的平面凸点式封装结构，包括芯片承载底座、打线内脚承载底座、芯片、金属线以及塑封体，所述的芯片承载底座包括中间基岛以及基岛正面活化物质、活化物质正面金属层，所述的打线内脚承载底座包括中间引脚以及引脚正面活化物质、活化物质正面金属层，芯片承载底座的正面金属层上涂布银胶，银胶上植入芯片，芯片正面和打线内脚承载底座正面金属层分别与金属线两端连接制成封装结构半成品，封装结构半成品正面用塑封体包封，并使基岛和引脚的背面凸出于塑封体表面，凸出塑封体的基岛表面镀有活化物质，活化物质表面镀有金属层，凸出塑封体的引脚表面镀有活化物质，活化物质表面镀有金属层。
本发明适用于集成电路或分立元件的平面凸点式封装工艺及其封装结构，其封装型式采用平面式凸点封装，阵列式集合体经切割成为单一的单元。其基板型式为在基板上半蚀刻以相对露出所需要的基岛和引脚。与四面无脚表面贴片式封装相比，本发明具有如下优点：
1、引线框：采用半蚀刻方式制作引线框。
2、化学胶膜：因采用半蚀刻方式，所以在包封过程中完全不会有溢料的产生，而且完全无需贴上防止溢料用的胶膜。
3、污染：无需使用任何化学胶膜却仍然可以防止包封过程中溢料的产生，所以完全不会有污染的问题，生产顺畅，良率提高，成本低廉。
4、金属丝焊线：平面式凸点封装结构中输出的焊点是凸出于塑封体表面的，此外两次蚀刻保证了焊点间的绝对共面性。如此单点独立的焊接方式可以维持目前一般芯片的焊性能力，也不用担心表面贴装是否会不稳定，品质比传统四面表面贴片式封装型式更加稳定。
5、可靠性
A.完全不会产生溢胶；
B.因采用半蚀刻的方式，所以在包封过程中采用再大的压力也不会有溢料产生，各项可靠性得以保障，而且生产更顺利，成本也会随之下降；
C平面凸点式封装型式其底部输出脚的部分是凸出塑封体的；同时，因为半蚀刻的方式，所以可以保证脚掌绝对共面；
D.因塑封体底部的输出脚是凸出塑封体0.05±0.025mm的尺寸，其锡膏残余量会附着在凸脚的四周，不容易产生锡膏短路，进而增加了凸脚焊点的焊接能力；
E.打线区的内脚可不采用镀银层而改用镀金层、镀镍层或镀镍钯层，因为塑封料与金或镍、镍钯的结合能力比银好很多，进而不容易造成分层的困扰；
F.电性输出的外脚采用镀金层或镍层、镍钯层时，因为此材料属于惰性材料，不会因为环境中气体或温度而氧化，所以保存的时间非常长；
G.电性输出的外脚采用镀金层、镍层或镍钯层时，由于该材料都属于惰性金属材料，熔点较高，所以不会因为切割时的磨擦生热而造成焊点的氧化甚至是熔化，从而保证了输出脚的可焊性及电性传输的稳定性，而产品品质得以很好的保证。
6、散热性、导电率：可采用纯铜的工艺，因为平面式凸点封装的引线框是采用基板半蚀刻的方式，所以其引线框的强度与结构相对于穿透式蚀刻的引线框至少高出一倍；同时，导电率/散热性也至少提升30％以上，从而产品的电性传输速率也快速很多。
附图说明：
图1～18分别为本发明适用于集成电路或分立元件的平面凸点式封装工艺各工序示意图。
图19为本发明集成电路或分立元件的平面凸点式封装结构示意图。
具体实施方式：
本发明适用于集成电路或分立元件的平面凸点式封装工艺如下：
1)基板——参见图1，取一片厚度合适的金属基板1。金属基板1的材质可以依据芯片的功能与特性进行变换，例如：镍铁合金、纯铜或铜合金等。
2)贴覆干膜——参见图2，在金属基板的两面各自贴上干膜层2、3，以保护后续的蚀刻工艺作业。
3)去除部分干膜——参见图3，在金属基板1的两面对应去除部分干膜，在金属基板1上准备形成基岛及引脚，用意是露出基板上后续需要镀活化物质的区域，
4)镀活化物质——参见图4，在金属基板1上准备形成的基岛及引脚区域的两面都镀上活化物质4.1、4.2、5.1、5.2；
5)镀金属层——参见图5，在金属基板1上准备形成的基岛及引脚区域两面的活化物质上都镀上金属层6.1、6.2、7.1、7.2，例如金、银、铜、锡、镍、镍钯等，以利后续焊线时金属线与芯片区和打线内脚区之间能更加紧密、牢固的接合，同时增加与塑封料饼间的结合度，
6)去除基板正面剩余的干膜——参见图6，去除金属基板正面剩余的干膜3。
7)基板正面半蚀刻——参见图7，对去除了金属基板1正面余下的干膜的区域进行半蚀刻，在金属基板1上形成凹陷的半蚀刻区1.3，同时相对形成基岛及引脚1.1、1.2，其用意主要是避免在后续作业中出现溢胶。
8)去除基板背面剩余的干膜——参见图8，去除基板背面剩余的干膜层。
9)银胶涂布——参见图9，在芯片区的金属层6.1上涂上银胶8(导电胶/非导电胶)。如果采用共晶的方式，则无需涂布银胶。
10)贴片作业——参见图10，在刚刚完成银胶涂布的芯片区域进行芯片9的植入，完成后再依据银胶的特性进行银胶后固化的作业，制成适用于集成电路或分立元件的的陈列式集合体半成品。
11)金属线球焊——参见图11，依据产品特性，对已完成芯片植入作业的半成品进行打金属线10作业，金属线材有金线、银线、铜线或铝线。
12)包封作业——参见图12，将已打线完成的半成品正面进行包封塑封体11作业，并依据塑封料的特性进行塑料包封后固化作业，以保护金属线、芯片及内脚的安全。
13)打印作业——参见图13，将已完成塑料包封及后固化作业的半成品，进行正面打印12作业，用以识别芯片的功能及特性。
14)基板背面蚀刻——参见图14，在金属基板的背面对不被金属层覆盖的区域即半蚀刻区剩余部分的金属1.4再次进行蚀刻工艺作业，以使基岛和引脚的背面凸出塑封体11。
15)塑封体粘贴作业——参见图15，将半成品的塑封体正面贴上胶膜13，准备进行后续的胶体切割作业。
16)塑封体切割——参见图16，利用切割机对已贴上胶膜的半成品进行切割作业，使原本以阵列式集合体方式连在一起的芯片一颗颗独立开来。
17)塑封体与粘胶膜分离——参见图17，将完成切割的产品利用取放转换设备将单颗适用于集成电路或分立元件的的塑封体逐一的吸出胶膜，并置放于塑料承载盘、塑料承载胶管、编带内。
18)最后成品——参见图18，图中14为芯片放置区，15为功能脚。
参见图19，集成电路或分立元件平面凸点式封装结构，主要由芯片承载底座16、打线内脚承载底座17、芯片9、金属线10以及塑封体11组成。
所述的芯片承载底座16包括中间基岛1.1以及基岛正面活化物质4.1、活化物质4.1正面金属层6.1，所述的打线内脚承载底座17包括中间引脚1.2以及引脚正面活化物质4.2、活化物质4.2正面金属层6.2，芯片承载底座16的正面金属层6.1上涂布银胶8，银胶8上植入芯片9，芯片9正面和打线内脚承载底座17正面金属层6.2分别与金属线10两端连接制成封装结构半成品，封装结构半成品正面用塑封体11包封，并使基岛1.1和引脚1.2的背面凸出于塑封体11表面，凸出塑封体11的基岛1.1表面镀有活化物质5.1，活化物质5.1表面镀有金属层7.1，凸出塑封体11的引脚1.2表面镀有活化物质5.2，活化物质5.2表面镀有金属层7.2。

Claims (9)

1.一种适用于集成电路或分立元件的平面凸点式封装工艺，其特征在于它包括以下工艺步骤：
——取一片金属基板(1)，
——在金属基板(1)的正、背两面各自贴上干膜层(2、3)，
——将金属基板(1)上层的部分干膜去除掉，在金属基板(1)上准备形成基岛及引脚，
——在金属基板(1)上准备形成的基岛及引脚区域的正面镀上活化物质(4.3、4.4)，
——在金属基板(1)上准备形成的基岛及引脚区域正面的活化物质(4.3、4.4)上镀上金属层(4.1、4.2)，
——去除金属基板(1)上层余下的干膜，
——对去除了金属基板(1)上层余下的干膜的区域进行半蚀刻，在金属基板(1)上形成凹陷的半蚀刻区(1.3)，同时相对形成基岛(1.1)及引脚(1.2)，
——去除基板背面的干膜层(3)，
——在金属基板(1)的基岛(1.1)正面金属层(4.1)上进行芯片(6)的植入，制成集成电路或分立元件的阵列式集合体半成品，
——将已完成芯片植入作业的半成品进行打金属线(7)作业，
——将已打线完成的半成品正面进行包封塑封体(8)作业，并进行塑料包封后固化作业，
——将已完成塑料包封及后固化作业的半成品，进行正面打印(12)作业，
——在金属基板(1)的背面对不被金属层覆盖的区域即半蚀刻区(1.3)余下部分的金属(1.4)再次进行蚀刻，从而使基岛(1.1)及引脚(1.2)的背面凸出于塑封体(11)，
——将塑封体(11)正面贴上胶膜(13)，
——对已贴上胶膜的半成品进行切割作业，使原本以阵列式集合体方式连在一起的芯片一颗颗独立开来，
——将完成切割的产品利用取放转换设备将单颗适用于集成电路或分立元件的的塑封体吸出胶膜。
2.根据权利要求1所述的一种适用于集成电路或分立元件的平面凸点式封装工艺，其特征在于在基岛(1.1)正面金属层(6.1)上直接进行芯片(9)的植入。
3.根据权利要求1所述的一种适用于集成电路或分立元件的平面凸点式封装工艺，其特征在于先在基岛(1.1)正面金属层(6.1)上涂布上银胶(8)，再在刚刚完成银胶涂布的银胶(8)上进行芯片(9)的植入，完成后再进行银胶后固化的作业。
4.根据权利要求1或2、3所述的一种适用于集成电路或分立元件的平面凸点式封装工艺，其特征在于镀在基岛(1.1)及引脚(1.2)上面的所述金属层(6.1、6.2)为金或银、铜、镍、镍钯层。
5.根据权利要求1或2、3所述的一种适用于集成电路或分立元件的平面凸点式封装工艺，其特征在于镀在基岛(1.1)及引脚(1.2)下面的所述金属层(7.1、7.2)为金或银、铜、锡、镍、镍钯层。
6.根据权利要求1或2、3所述的一种适用于集成电路或分立元件的平面凸点式封装工艺，其特征在于金属线(10)为金线或银线、铜线、铝线。
7.一种适用于集成电路或分立元件的平面凸点式封装结构，包括芯片承载底座(16)、打线内脚承载底座(17)、芯片(9)、金属线(10)以及塑封体(11)，其特征在于：所述的芯片承载底座(16)包括中间基岛(1.1)以及基岛正面活化物质(4.1)、活化物质(4.1)正面金属层(6.1)，所述的打线内脚承载底座(17)包括中间引脚(1.2)以及引脚正面活化物质(4.2)、活化物质(4.2)正面金属层(6.2)，芯片承载底座(16)的正面金属层(6.1)上植入芯片(9)，芯片(9)正面和打线内脚承载底座(17)正面金属层(6.2)分别与金属线(10)两端连接制成封装结构半成品，封装结构半成品正面用塑封体(11)包封，并使基岛(1.1)和引脚(1.2)的背面凸出于塑封体(11)表面，凸出塑封体(11)的基岛(1.1)表面镀有活化物质(5.1)，活化物质(5.1)表面镀有金属层(7.1)，凸出塑封体(11)的引脚(1.2)表面镀有活化物质(5.2)，活化物质(5.2)表面镀有金属层(7.2)。
8.根据权利要求7所述的一种适用于集成电路或分立元件的平面凸点式封装结构，其特征在于芯片承载底座(16)正面金属层(6.1)上直接进行芯片(9)的植入。
9.根据权利要求7所述的一种适用于集成电路或分立元件的平面凸点式封装结构，其特征在于芯片承载底座(16)正面金属层(6.1)上先涂布一层银胶层(8)，再在银胶层(8)上植入芯片(9)。
CNB2005100412746A 2005-04-07 2005-07-18 适用于集成电路或分立元件的平面凸点式封装工艺 Active CN100376021C (zh)

Priority Applications (8)

Application Number Priority Date Filing Date Title
CNB2005100412746A CN100376021C (zh) 2005-07-18 2005-07-18 适用于集成电路或分立元件的平面凸点式封装工艺
PCT/CN2006/000608 WO2006105734A1 (en) 2005-04-07 2006-04-06 A packaging substrate with flat bumps for electronic devices and method of manufacturing the same
PCT/CN2006/000607 WO2006105733A1 (en) 2005-04-07 2006-04-06 Package structure with flat bumps for electronic device and method of manufacture the same
PCT/CN2006/000609 WO2006105735A1 (en) 2005-04-07 2006-04-06 Package structure with flat bumps for integrate circuit or discrete device and method of manufacture the same
PCT/CN2006/000610 WO2006122467A1 (en) 2005-04-07 2006-04-06 A packaging substrate with flat bumps for ic or discrete device and method of manufacturing the same
US11/910,893 US20080285251A1 (en) 2005-04-07 2006-04-06 Packaging Substrate with Flat Bumps for Electronic Devices and Method of Manufacturing the Same
US11/910,885 US20080315412A1 (en) 2005-04-07 2006-04-06 Package Structure with Flat Bumps for Integrate Circuit or Discrete Device and Method of Manufacture the Same
US11/910,878 US20080258273A1 (en) 2005-04-07 2006-04-06 Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100412746A CN100376021C (zh) 2005-07-18 2005-07-18 适用于集成电路或分立元件的平面凸点式封装工艺

Publications (2)

Publication Number Publication Date
CN1738014A CN1738014A (zh) 2006-02-22
CN100376021C true CN100376021C (zh) 2008-03-19

Family

ID=36080756

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100412746A Active CN100376021C (zh) 2005-04-07 2005-07-18 适用于集成电路或分立元件的平面凸点式封装工艺

Country Status (1)

Country Link
CN (1) CN100376021C (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035535A (zh) * 2012-12-26 2013-04-10 常州银河世纪微电子有限公司 大电流/高压二极管的制备方法
CN105789151A (zh) * 2016-03-30 2016-07-20 华天科技（西安）有限公司 一种切割式多圈qfn/dfn封装件及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866867B (zh) * 2010-06-18 2012-08-22 日月光封装测试(上海)有限公司 无外引脚半导体封装构造的导线架制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015638A (ja) * 1999-06-30 2001-01-19 Mitsumi Electric Co Ltd Ｉｃパッケージの基板
US6521987B1 (en) * 1998-10-21 2003-02-18 Amkor Technology, Inc. Plastic integrated circuit device package and method for making the package
CN1599046A (zh) * 2004-08-09 2005-03-23 江苏长电科技股份有限公司 集成电路或分立元件超薄无脚封装工艺及其封装结构
CN2836239Y (zh) * 2005-07-18 2006-11-08 江苏长电科技股份有限公司 集成电路或分立元件平面凸点式封装结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521987B1 (en) * 1998-10-21 2003-02-18 Amkor Technology, Inc. Plastic integrated circuit device package and method for making the package
JP2001015638A (ja) * 1999-06-30 2001-01-19 Mitsumi Electric Co Ltd Ｉｃパッケージの基板
CN1599046A (zh) * 2004-08-09 2005-03-23 江苏长电科技股份有限公司 集成电路或分立元件超薄无脚封装工艺及其封装结构
CN2836239Y (zh) * 2005-07-18 2006-11-08 江苏长电科技股份有限公司 集成电路或分立元件平面凸点式封装结构

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035535A (zh) * 2012-12-26 2013-04-10 常州银河世纪微电子有限公司 大电流/高压二极管的制备方法
CN103035535B (zh) * 2012-12-26 2015-03-04 常州银河世纪微电子有限公司 大电流/高压二极管的制备方法
CN105789151A (zh) * 2016-03-30 2016-07-20 华天科技（西安）有限公司 一种切割式多圈qfn/dfn封装件及其制造方法

Also Published As

Publication number Publication date
CN1738014A (zh) 2006-02-22

Similar Documents

Publication Publication Date Title
CN100369223C (zh) 集成电路或分立元件平面凸点式封装工艺及其封装结构
WO2006105735A1 (en) Package structure with flat bumps for integrate circuit or discrete device and method of manufacture the same
CN103022021B (zh) 半导体装置及其制造方法
CN102005432B (zh) 四面无引脚封装结构及其封装方法
KR100470897B1 (ko) 듀얼 다이 패키지 제조 방법
CN103403864B (zh) 具有凝聚端子的半导体封装体
CN100568498C (zh) 半导体器件及其制造方法
US20010034082A1 (en) Semiconductor package and semiconductor package fabrication method
CN111584478B (zh) 一种叠层芯片封装结构和叠层芯片封装方法
CN102165581A (zh) 引线框基板的制造方法及半导体装置
CN100376021C (zh) 适用于集成电路或分立元件的平面凸点式封装工艺
CN100359655C (zh) 集成电路或分立元件平面凸点式封装工艺
CN100481420C (zh) 堆叠型芯片封装结构、芯片封装体及其制造方法
CN208796987U (zh) 一种引线框架及其超薄型小外形倒装封装件
CN100337317C (zh) 适用于集成电路或分立元件的平面凸点式封装工艺及其封装结构
CN100370589C (zh) 新型集成电路或分立元件超薄无脚封装工艺
CN102263077A (zh) 一种双扁平无载体无引脚的ic芯片封装件
CN207183254U (zh) 一种提高bga产品可靠性的封装结构
CN111192835A (zh) 芯片封装方法和芯片封装结构
CN101131992A (zh) 多芯片堆栈式的封装结构
CN202196776U (zh) 一种扁平无载体无引线引脚外露封装件
CN2836239Y (zh) 集成电路或分立元件平面凸点式封装结构
CN2819476Y (zh) 新型集成电路或分立元件平面凸点式封装结构
JP2011049298A (ja) 半導体装置の製造方法
KR20080086178A (ko) 스택 패키지 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20161230

Address after: The 300000 Tianjin FTA test area (Dongjiang Bonded Port) No. 6865 North Road, 1-1-1802-7 financial and trade center of Asia

Patentee after: Xin Xin finance leasing (Tianjin) Co.,Ltd.

Address before: 214431 Binjiang Middle Road, Jiangsu, China, No. 275, No.

Patentee before: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

EE01 Entry into force of recordation of patent licensing contract

Application publication date: 20060222

Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

Assignor: Xin Xin finance leasing (Tianjin) Co.,Ltd.

Contract record no.: 2017320000152

Denomination of invention: Novel integrated circuit or discrete component flat bump package technics and its package structure

Granted publication date: 20080319

License type: Exclusive License

Record date: 20170614

EE01 Entry into force of recordation of patent licensing contract
EC01 Cancellation of recordation of patent licensing contract

Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

Assignor: Xin Xin finance leasing (Tianjin) Co.,Ltd.

Contract record no.: 2017320000152

Date of cancellation: 20200416

EC01 Cancellation of recordation of patent licensing contract
TR01 Transfer of patent right

Effective date of registration: 20200423

Address after: 214434, No. 78, mayor road, Chengjiang, Jiangsu, Jiangyin, Wuxi

Patentee after: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

Address before: 1-1-1802-7, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin pilot free trade zone (Dongjiang Free Trade Port Area)

Patentee before: Xin Xin finance leasing (Tianjin) Co.,Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20221114

Address after: 201201 room 111, building 1, No. 200, Jichuang Road, Pudong New Area, Shanghai

Patentee after: Changdian Technology Management Co.,Ltd.

Address before: No.78 Changshan Road, Chengjiang Town, Jiangyin City, Wuxi City, Jiangsu Province

Patentee before: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

TR01 Transfer of patent right