CN100355043C - 具有金属栅极电极的半导体装置及其制程 - Google Patents

具有金属栅极电极的半导体装置及其制程 Download PDF

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Publication number
CN100355043C
CN100355043C CNB02823443XA CN02823443A CN100355043C CN 100355043 C CN100355043 C CN 100355043C CN B02823443X A CNB02823443X A CN B02823443XA CN 02823443 A CN02823443 A CN 02823443A CN 100355043 C CN100355043 C CN 100355043C
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silicon
gate electrode
metal gate
silicon oxynitride
supply
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CN1592959A (zh
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M·V·恩戈
A·哈里亚
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/308Oxynitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
CNB02823443XA 2001-11-26 2002-10-11 具有金属栅极电极的半导体装置及其制程 Expired - Fee Related CN100355043C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/994,128 2001-11-26
US09/994,128 US6509282B1 (en) 2001-11-26 2001-11-26 Silicon-starved PECVD method for metal gate electrode dielectric spacer

Publications (2)

Publication Number Publication Date
CN1592959A CN1592959A (zh) 2005-03-09
CN100355043C true CN100355043C (zh) 2007-12-12

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CNB02823443XA Expired - Fee Related CN100355043C (zh) 2001-11-26 2002-10-11 具有金属栅极电极的半导体装置及其制程

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US (2) US6509282B1 (enExample)
EP (1) EP1449243A1 (enExample)
JP (1) JP2005510872A (enExample)
KR (1) KR100891367B1 (enExample)
CN (1) CN100355043C (enExample)
AU (1) AU2002347877A1 (enExample)
WO (1) WO2003046971A1 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4659329B2 (ja) * 2000-06-26 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US20040212025A1 (en) * 2003-04-28 2004-10-28 Wilman Tsai High k oxide
JP4511307B2 (ja) * 2004-02-10 2010-07-28 セイコーエプソン株式会社 ゲート絶縁膜、半導体素子、電子デバイスおよび電子機器
US7102191B2 (en) * 2004-03-24 2006-09-05 Micron Technologies, Inc. Memory device with high dielectric constant gate dielectrics and metal floating gates
JP4876375B2 (ja) * 2004-07-06 2012-02-15 ソニー株式会社 半導体装置およびその製造方法
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
KR100688575B1 (ko) * 2004-10-08 2007-03-02 삼성전자주식회사 비휘발성 반도체 메모리 소자
US20060094194A1 (en) * 2004-11-04 2006-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology
US7732923B2 (en) * 2004-12-30 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Impurity doped UV protection layer
KR100771808B1 (ko) * 2006-07-05 2007-10-30 주식회사 하이닉스반도체 Sonos 구조를 갖는 플래시 메모리 소자 및 그것의제조 방법
KR100819706B1 (ko) * 2006-12-27 2008-04-04 동부일렉트로닉스 주식회사 씨모스 이미지센서 및 그 제조방법
DE202007001431U1 (de) * 2007-01-31 2007-05-16 Infineon Technologies Austria Ag Halbleiteranordnung und Leistungshalbleiterbauelement
JP5358893B2 (ja) * 2007-04-03 2013-12-04 三菱電機株式会社 トランジスタ
US20080246099A1 (en) * 2007-04-09 2008-10-09 Ajith Varghese Low temperature poly oxide processes for high-k/metal gate flow
CN102157360B (zh) * 2010-02-11 2012-12-12 中芯国际集成电路制造(上海)有限公司 一种栅极制造方法
US8936965B2 (en) * 2010-11-26 2015-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8822283B2 (en) 2011-09-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned insulated film for high-k metal gate device
KR102309244B1 (ko) 2013-02-20 2021-10-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
TWI695525B (zh) 2014-07-25 2020-06-01 日商半導體能源研究所股份有限公司 剝離方法、發光裝置、模組以及電子裝置
US11223289B2 (en) 2020-01-17 2022-01-11 Astec International Limited Regulated switched mode power supplies having adjustable output voltages
CN111540673B (zh) * 2020-07-07 2020-10-16 中芯集成电路制造(绍兴)有限公司 半导体器件的形成方法
KR102608390B1 (ko) 2021-07-06 2023-12-01 한국과학기술연구원 내구성이 우수한 컬러링 금속 부재 및 이의 제조방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441247A (en) * 1981-06-29 1984-04-10 Intel Corporation Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
US4648175A (en) * 1985-06-12 1987-03-10 Ncr Corporation Use of selectively deposited tungsten for contact formation and shunting metallization
US5300455A (en) * 1990-12-13 1994-04-05 France Telecom Process for producing an electrically conductive diffusion barrier at the metal/silicon interface of a MOS transistor
CN1266277A (zh) * 1999-02-26 2000-09-13 德克萨斯仪器股份有限公司 形成cmos器件的双金属栅结构的方法

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US444124A (en) * 1891-01-06 Matrix making machine
JPS63184340A (ja) * 1986-09-08 1988-07-29 Nec Corp 半導体装置
JPS63316476A (ja) 1987-06-18 1988-12-23 Seiko Instr & Electronics Ltd 半導体装置およびその製造方法
US4854263B1 (en) 1987-08-14 1997-06-17 Applied Materials Inc Inlet manifold and methods for increasing gas dissociation and for PECVD of dielectric films
JPH01173635A (ja) * 1987-12-28 1989-07-10 Nissan Motor Co Ltd 半導体装置の製造方法
GB2244860A (en) 1990-06-04 1991-12-11 Philips Electronic Associated Fabricating mim type device array and display devices incorporating such arrays
JPH04209543A (ja) * 1990-12-06 1992-07-30 Seiko Instr Inc 半導体装置の製造方法
JP2506539B2 (ja) * 1992-02-27 1996-06-12 株式会社ジーティシー 絶縁膜の形成方法
GB9206086D0 (en) 1992-03-20 1992-05-06 Philips Electronics Uk Ltd Manufacturing electronic devices comprising,e.g.tfts and mims
JP2722989B2 (ja) * 1993-04-27 1998-03-09 日本電気株式会社 配線の埋め込み方法
DE69433836D1 (de) * 1993-12-28 2004-07-15 Applied Materials Inc Verfahren zur plasma-unterstützten chemischen Dampfabscheidung von Silizium-Oxynitridschichten
US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
NZ280375A (en) 1996-05-01 1998-09-24 Ind Res Ltd A silicon oxynitride ceramic material characterised by its x-ray powder diffraction trace
TW320752B (en) 1996-11-18 1997-11-21 United Microelectronics Corp Metal gate electrode process
US5930627A (en) 1997-05-05 1999-07-27 Chartered Semiconductor Manufacturing Company, Ltd. Process improvements in self-aligned polysilicon MOSFET technology using silicon oxynitride
US5989957A (en) 1997-05-21 1999-11-23 Advanced Micro Devices Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration
US6187656B1 (en) 1997-10-07 2001-02-13 Texas Instruments Incorporated CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes
US6140190A (en) * 1997-12-18 2000-10-31 Advanced Micro Devices Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors
US6051487A (en) 1997-12-18 2000-04-18 Advanced Micro Devices, Inc. Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode
US6274421B1 (en) 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
US6225168B1 (en) 1998-06-04 2001-05-01 Advanced Micro Devices, Inc. Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof
US6200734B1 (en) * 1998-06-15 2001-03-13 Lucent Technologies Inc. Method for fabricating semiconductor devices
US6107171A (en) 1998-07-09 2000-08-22 Vanguard International Semiconductor Corporation Method to manufacture metal gate of integrated circuits
US6110779A (en) 1998-07-17 2000-08-29 Advanced Micro Devices, Inc. Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
US6100559A (en) * 1998-08-14 2000-08-08 Advanced Micro Devices, Inc. Multipurpose graded silicon oxynitride cap layer
JP2000091337A (ja) * 1998-09-09 2000-03-31 Toshiba Microelectronics Corp 半導体装置及びその製造方法
US6066533A (en) 1998-09-29 2000-05-23 Advanced Micro Devices, Inc. MOS transistor with dual metal gate structure
US6245605B1 (en) 1998-09-29 2001-06-12 Texas Instruments Incorporated Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing
US6162694A (en) 1998-11-25 2000-12-19 Advanced Micro Devices, Inc. Method of forming a metal gate electrode using replaced polysilicon structure
US6221794B1 (en) * 1998-12-08 2001-04-24 Advanced Micro Devices, Inc. Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines
KR100300628B1 (ko) * 1999-02-08 2001-09-26 윤종용 실리콘 옥시나이트라이드 보호층을 갖는 반도체 장치 및 그 제조 방법
US6096656A (en) 1999-06-24 2000-08-01 Sandia Corporation Formation of microchannels from low-temperature plasma-deposited silicon oxynitride
US6046103A (en) * 1999-08-02 2000-04-04 Taiwan Semiconductor Manufacturing Company Borderless contact process for a salicide devices
JP4243401B2 (ja) * 1999-12-21 2009-03-25 エルジー ディスプレイ カンパニー リミテッド 銅配線基板およびその製造方法ならびに液晶表示装置
US6372668B2 (en) * 2000-01-18 2002-04-16 Advanced Micro Devices, Inc. Method of forming silicon oxynitride films
US6670695B1 (en) * 2000-02-29 2003-12-30 United Microelectronics Corp. Method of manufacturing anti-reflection layer
JP2001308086A (ja) * 2000-04-18 2001-11-02 Nec Corp 膜形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441247A (en) * 1981-06-29 1984-04-10 Intel Corporation Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
US4648175A (en) * 1985-06-12 1987-03-10 Ncr Corporation Use of selectively deposited tungsten for contact formation and shunting metallization
US5300455A (en) * 1990-12-13 1994-04-05 France Telecom Process for producing an electrically conductive diffusion barrier at the metal/silicon interface of a MOS transistor
CN1266277A (zh) * 1999-02-26 2000-09-13 德克萨斯仪器股份有限公司 形成cmos器件的双金属栅结构的方法

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US6605848B2 (en) 2003-08-12
JP2005510872A (ja) 2005-04-21
US20030098487A1 (en) 2003-05-29
AU2002347877A1 (en) 2003-06-10
US6509282B1 (en) 2003-01-21
EP1449243A1 (en) 2004-08-25
KR20040060991A (ko) 2004-07-06
WO2003046971A1 (en) 2003-06-05
KR100891367B1 (ko) 2009-04-02
CN1592959A (zh) 2005-03-09

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Patentee after: Globalfoundries Semiconductor Inc.

Address before: American California

Patentee before: Advanced Micro Devices Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20071212

Termination date: 20161011