CH631597B - Registre a decalage integre. - Google Patents

Registre a decalage integre.

Info

Publication number
CH631597B
CH631597B CH618779A CH618779A CH631597B CH 631597 B CH631597 B CH 631597B CH 618779 A CH618779 A CH 618779A CH 618779 A CH618779 A CH 618779A CH 631597 B CH631597 B CH 631597B
Authority
CH
Switzerland
Prior art keywords
register
plate
offset register
output electrode
integrated offset
Prior art date
Application number
CH618779A
Other languages
English (en)
French (fr)
Other versions
CH631597GA3 (enrdf_load_stackoverflow
Inventor
Jakob Luescher
Original Assignee
Ebauches Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication of CH631597B publication Critical patent/CH631597B/fr
Application filed by Ebauches Sa filed Critical Ebauches Sa
Publication of CH631597GA3 publication Critical patent/CH631597GA3/fr

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/46Out-of-phase gating or clocking signals applied to counter stages using charge transfer devices, i.e. bucket brigade or charge coupled devices
    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G3/00Producing timing pulses
    • G04G3/02Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/025Circuits for deriving low frequency timing pulses from pulses of higher frequency by storing time-date which are periodically investigated and modified accordingly, e.g. by using cyclic shift-registers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G11C19/186Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET using only one transistor per capacitor, e.g. bucket brigade shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
CH618779A 1978-07-06 1979-07-03 Registre a decalage integre. CH631597B (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7820163A FR2430649A1 (fr) 1978-07-06 1978-07-06 Registre a decalage integre

Publications (2)

Publication Number Publication Date
CH631597B true CH631597B (fr)
CH631597GA3 CH631597GA3 (enrdf_load_stackoverflow) 1982-08-31

Family

ID=9210404

Family Applications (1)

Application Number Title Priority Date Filing Date
CH618779A CH631597B (fr) 1978-07-06 1979-07-03 Registre a decalage integre.

Country Status (5)

Country Link
JP (1) JPS5950231B2 (enrdf_load_stackoverflow)
CH (1) CH631597B (enrdf_load_stackoverflow)
DE (1) DE2919970C2 (enrdf_load_stackoverflow)
FR (1) FR2430649A1 (enrdf_load_stackoverflow)
GB (1) GB2027302B (enrdf_load_stackoverflow)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1541921B2 (de) * 1967-09-19 1972-01-05 Fernseh Gmbh, 6100 Darmstadt Schaltungsanordnung zum verzoegern von analogsignalen
US3643106A (en) * 1970-09-14 1972-02-15 Hughes Aircraft Co Analog shift register
NL165869C (nl) * 1970-09-25 1981-05-15 Philips Nv Analoog schuifregister.
US3763480A (en) * 1971-10-12 1973-10-02 Rca Corp Digital and analog data handling devices
US3812520A (en) * 1972-08-24 1974-05-21 Gen Instrument Corp Parasitic transistor shift register

Also Published As

Publication number Publication date
FR2430649A1 (fr) 1980-02-01
DE2919970C2 (de) 1984-08-02
JPS5536989A (en) 1980-03-14
DE2919970A1 (de) 1980-01-17
JPS5950231B2 (ja) 1984-12-07
GB2027302B (en) 1982-06-16
CH631597GA3 (enrdf_load_stackoverflow) 1982-08-31
FR2430649B1 (enrdf_load_stackoverflow) 1982-02-05
GB2027302A (en) 1980-02-13

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Legal Events

Date Code Title Description
PL Patent ceased