JPS5556734A - Frequency converting circuit - Google Patents

Frequency converting circuit

Info

Publication number
JPS5556734A
JPS5556734A JP12981478A JP12981478A JPS5556734A JP S5556734 A JPS5556734 A JP S5556734A JP 12981478 A JP12981478 A JP 12981478A JP 12981478 A JP12981478 A JP 12981478A JP S5556734 A JPS5556734 A JP S5556734A
Authority
JP
Japan
Prior art keywords
signal
register
output
input
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12981478A
Other languages
Japanese (ja)
Inventor
Hiroichi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12981478A priority Critical patent/JPS5556734A/en
Publication of JPS5556734A publication Critical patent/JPS5556734A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/40Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/406Synchronisation of counters

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To ensure an easy conversion for the frequency in a simple constitution by reading the FF output signal by the conversion signal applied to the clock input of the register and sending the digit output to the OR gate with every second register at least. CONSTITUTION:Converted signal S1 is supplied to clock input T of FF12, and its reverse Q output Q' is supplied to the data input D as well as to serial input INS of shift register 13. Here register 13 reads the output signal of FF12 according to conversion signal S2 supplied to clock input T, and OR gate 14 is provided to give the OR input for the digit output of at least every second order of register 13. Thus signal SO which is synchronized with signal S2 and then converted signal S1 into the fixed ratio is delivered. In such way, the frequency can be converted easily in a simple constitution.
JP12981478A 1978-10-20 1978-10-20 Frequency converting circuit Pending JPS5556734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12981478A JPS5556734A (en) 1978-10-20 1978-10-20 Frequency converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12981478A JPS5556734A (en) 1978-10-20 1978-10-20 Frequency converting circuit

Publications (1)

Publication Number Publication Date
JPS5556734A true JPS5556734A (en) 1980-04-25

Family

ID=15018872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12981478A Pending JPS5556734A (en) 1978-10-20 1978-10-20 Frequency converting circuit

Country Status (1)

Country Link
JP (1) JPS5556734A (en)

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