JPS558656A - Sample hold circuit - Google Patents

Sample hold circuit

Info

Publication number
JPS558656A
JPS558656A JP8133978A JP8133978A JPS558656A JP S558656 A JPS558656 A JP S558656A JP 8133978 A JP8133978 A JP 8133978A JP 8133978 A JP8133978 A JP 8133978A JP S558656 A JPS558656 A JP S558656A
Authority
JP
Japan
Prior art keywords
capacitor
switch
dependent
operational amplifier
bias current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8133978A
Other languages
Japanese (ja)
Inventor
Shinzo Koo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8133978A priority Critical patent/JPS558656A/en
Publication of JPS558656A publication Critical patent/JPS558656A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE: To reduce the fluctuation of an output voltage dependent upon a bias current at a hold time by adding a capacitor and a switch to an operational amplifier.
CONSTITUTION: Capacitor 10 to cancel the voltage fluctuation of capacitor 2 dependent upon the bias current at input end 6 of operational amplifier 1 with the self- voltage fluctuation dependent upon the bias current at input end 7 of operational amplifier 1 during a hold period and switch 11 which is connected in parallel to capacitor 10 and is switched synchronously with switch 3 are added. Then, the output voltage fluctuation during a hold period is restrained.
COPYRIGHT: (C)1980,JPO&Japio
JP8133978A 1978-07-04 1978-07-04 Sample hold circuit Pending JPS558656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8133978A JPS558656A (en) 1978-07-04 1978-07-04 Sample hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8133978A JPS558656A (en) 1978-07-04 1978-07-04 Sample hold circuit

Publications (1)

Publication Number Publication Date
JPS558656A true JPS558656A (en) 1980-01-22

Family

ID=13743604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8133978A Pending JPS558656A (en) 1978-07-04 1978-07-04 Sample hold circuit

Country Status (1)

Country Link
JP (1) JPS558656A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5982699A (en) * 1982-09-29 1984-05-12 ウエスターン　エレクトリック　カムパニー，インコーポレーテツド Circuit and method for sample-holding signal
JPS60169800U (en) * 1984-04-17 1985-11-11 株式会社アドバンテスト Sample/hold circuit
JPS62195798A (en) * 1986-02-24 1987-08-28 Sony Corp Sample holding circuit
JPS6424599U (en) * 1987-08-03 1989-02-09
JPS6470997A (en) * 1987-08-12 1989-03-16 Honeywell Inc Amplifier device interchangeable between operational mode
US5570048A (en) * 1992-10-19 1996-10-29 U.S. Philips Corporation Sample-and-hold circuit with reduced clock feedthrough

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5982699A (en) * 1982-09-29 1984-05-12 ウエスターン　エレクトリック　カムパニー，インコーポレーテツド Circuit and method for sample-holding signal
JPH057800B2 (en) * 1982-09-29 1993-01-29 Ei Teii Ando Teii Tekunorojiizu Inc
JPS60169800U (en) * 1984-04-17 1985-11-11 株式会社アドバンテスト Sample/hold circuit
JPS62195798A (en) * 1986-02-24 1987-08-28 Sony Corp Sample holding circuit
JPS6424599U (en) * 1987-08-03 1989-02-09
JPS6470997A (en) * 1987-08-12 1989-03-16 Honeywell Inc Amplifier device interchangeable between operational mode
US5570048A (en) * 1992-10-19 1996-10-29 U.S. Philips Corporation Sample-and-hold circuit with reduced clock feedthrough

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