GB2027302A

GB2027302A - Integrated shift register

Info

Publication number: GB2027302A
Application number: GB7921507A
Authority: GB
Original assignee: Ebauches SA
Current assignee: Ebauches SA
Priority date: 1978-07-06
Filing date: 1979-06-20
Publication date: 1980-02-13
Also published as: GB2027302B; FR2430649B1; DE2919970C2; JPS5950231B2; FR2430649A1; JPS5536989A; DE2919970A1; CH631597B; CH631597GA3

Abstract

The shift register has a very low power consumption. Each cell of the register is constituted by two stages, each comprising an MOS structure (T1-T'1) which has two principal electrodes (Z00, Z1) respectively forming the input (Z00) and the output (Z1) of the stage, and two control electrodes (k1, k'1), one of which (k1) can be connected to a bias source (P) and the other of which (k'1) is connected to the output electrode (Z1), and a capacitor (C1) one plate (Z1) of which is connected to the said output electrode (Z1) and the other plate (C1) of which receives one of two periodic signals ???1 (t) and ???2 (t) in phase opposition. The register is especially useful in a frequency divider circuit. <IMAGE>

Description

SPECIFICATION Integrated shift register The present invention concerns an integrated shift register with very low power consumption. Such a register is particularly well suited, though this does not constitute its only field of application, to the construction of a frequency divider circuit usable in any type of small-sized portable device, powered by a battery which is required to ensure the unit's supply with a life time of up to several years.

As is known, the problem of energy consumption occurs most acutely when the frequency to be divided is high, even a few MHz, as is the case, for example, in high chronometric performance watches.

Attempts have been made to reduce energy consumption in frequency dividers by using C MOS integrated binary circuits. Most quartz watches are now equipped with such circuits.

in this instance, consumption is essentially determined by the charging and discharging of capacitances presented by each stage of the shift register and with the periodicity of its output signal. Each stage's consumption is consequently proportional to the value of its capacitances and to the frequency of its output signal. For a high frequency quartz watch, then, it is consequently the first stages, that is to say, those dividing the highest frequencies, which are determinative of the consumption of the electronics. In order to lower the capacitances of these stages, various manufacturing techniques, such as those known by the name of Si-gate or SOS (Silicon on sapphire) have been used.However, to keep consumption within acceptable limits, the dimensions of the integrated circuits have to be reduced to such a point that, in the current state of the art, the cost of their manufacture becomes prohibitive.

High frequency dividers with a large part of their capacitances forming part of a resonant circuit have also been proposed to lower power consumption. A system of this type is, for example, described in Swiss patent No.

558 111. In this instance, the energy stored periodically in the capacitances is recovered.

The system makes use of a shift register of a known type, realised in integrated form and designated an IGFET (insulated gate FET) bucket brigade register. This register is ring connected and a single charge packet is transferred from one cell to the other. Each cell comprises firstly two IGFET's which are connected in series, and two capacitors connected between the respective control electrodes and the transistor drains. The control electrodes are connected alternately to two lines supplied by a push-pull quartz oscillator supplying alternating voltages in phase opposition. Means are also provided to bias the crystalline substrate in which the circuits are integrated. The register cell presents a low load for the oscillator and the reactive current due to this capacitance causes a very small loss in the quartz.The principal real power which the oscillator has to supply is that dissipated in the transistor through which the transfer of the charge from one stage (halfcell) to the other is made.

The mode of operation of the shift register described above (and a detailed explanation o which is to be found in the article of C.N.

Berglund et al, "Fabrication and Performance Considerations of Charge-Transfer Dynamic Shift Registers", Bell System Technical Journal, Vol. 51, No. 3, March 1972) is such that the current goes through the transistor for about 1/4 period and the source-drain voltage of the latter changes during this time from practically the value Vp to O, Vp being the peak-to-peak value of the phase supply voltage supplied by the oscillator. Consequently, the power supplied by the oscillator, expressed by the general relation:

in which D (t) and VSD (t) are instantaneous values respectively of the drain current and of the source-drain voltage of the transistor, T being the oscillation period, then becomes PT= (Vp + v)2.C.f.

In this expression, C is the capacitance associated with the transistor, fis the oscillator frequency, and Vrn represents the average control voltage which exceeds the transistor threshold voltage. The voltage Vrn is normally a few tenths of volt, while vp is a few volts.

By taking a typical example with the values: Vp =2V,vm = 0.3 V, C = p F, and f = 42 MHz, a value of 2#2# W is obtained for PT.

The power supplied by the oscillator is consequently relatively high because of the high voltage necessary for the transfer of the charge packet from one cell of the register to the other.

The principal object of the present invention is to provide a shift register necessitating a very low voltage for charge transfer, which considerably reduces the power which has to be furnished by the oscillator.

According to the present invention, there is provided a shift register comprising a plurality of transistors and capacitors which are integrated in a semi-conductor substrate and form a plurality of cells connected one after the other, each cell comprising two identical stages connected in series and capable of being supplied by respective ones of two periodic signals in phase opposition, wherein each stage comprises an MOS transistor structure which has two principal electrodes forming respectively the input and output of the stage, and two control electrodes, one of which is connected, in use, to a bias source and the other of which is connected to the output electrode, and a capacitor, one plate of which is connected to the said output electrode and the other plate of which receives, in use, one of the said periodic signals, depending on the position of the cell in the register.

According to one advantageous embodiment of the invention, the transistor structure is consittuted by a MOS transistor with two control electrodes. Alternatively, this structure can be constituted by two MOS transistors in series.

The MOS transistor structure and the capacitor of each stage of the register are preferably formed by a first and second semi-conductor region of a type opposite to that of the substrate in which they are integrated, a first insulated conductor layer beginning above the first region and stopping substantially halfway between the first and second region, a second insulated conductor layer substantially beginning halfway between the first and the second region and stopping above the second region, a third conductor layer in contact with the second region and connected to the second conductor layer, and a fourth insulated conductor layer disposed opposite the second region.

The two semi-conductor regions form the principal electrodes of the structure whose first and second conductor layers form the control electrodes, and the fourth conductor layer forms a plate of the said capacitor whose second plate is formed by the second region.

As will appear more clearly in the description, the shift register which has just been briefly defined requires only a very low voltage for transferring its charge from one cell to the next. This considerably reduces the power which has to be supplied by the oscillator producing the two signals in phase opposition. As also appears later, the signals obtained on the various cells of the register are particularly well suited to the realisation of very low consumption frequency dividers.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 partially represents a shift register embodying the invention in schematic crosssection.

Figure 2 gives the equivalent diagram of a stage of the register in Fig. 1; and Figure 3 is a diagram serving to explain the functioning of the register in Fig. 1.

Reference will first be made to Fig. 1 in which an MOS structure has been represented which comprises a p type crystalline substrate, for example, in which five n type regions are integrated, respectively designated M', ZO, ZOO, Z1 and Z2 The whole is covered by an insulating layer I locally interrupted above part of the regions M', ZOO, Z and Z2 to allow deposition, directly on the n region concerned, of contacts m, aO, and a and b respectively.

The insulating layer I has deposited thereon a number of electrodes, designated respectively k, k' k1, Kt k2 and k'2, which principally extend above the p region. More precisely, the electrode k extends between the ends of the region M' and ZO, while the electrode K extends from the end of the region ZO to the beginning of the region ZOO where it is electrically connected to the contact at already mentioned.The electrode k, begins at the end of the region ZOO to stop virtually halfway between ZOD and Z,, partially overlapping the electrode K, which extends up to the beginning of the region Z, where it is electrically connected to the contact a Where the electrode k, overlaps the initial part of the electrode k', it is insulated therefrom by an insulating layer i. The electrodes k2-k'2 are disposed between the regions Z, and Z2 in the same way as the electrodes k, and K,.

Finally, the insulating layer I has thereon conducting deposits or electrodes cO, C1, Q, which extend above the regions Z00, Z1, and Z2 respectively. The electrode k is the electrode intended to receive the enabling signal through which a new charge packet is introduced into the register. This electrode is connected to an input terminal E.

The register is controlled by a push-pull oscillator (not represented), such as that described, for example, in Swiss patent No. 580 837, which supplies on the lines X and Y two sinusoidal voltages in phase opposition , (t) and +2 (t) respectively. The electrodes cO, c, and c2 are alternately connected to the lines X and Y. Additionally, the oscillator biases, by means of a voltage multiplier (not represented), like, for example, that described in Swiss patent No. 553 481, the crystalline substrate of the unit negatively in relation to a reference ground M' to which are connected, by a line P, the electrodes m, k1, and k2.

Thus, it is apparent that the integrated circuit in Fig. 1 is formed of an assembly of capacitors and MOS transistors. The electrodes cO, c, and C,, in fact constitute the plates of the capacitors CO, C, and C2 respectively, whose other plates are formed by the regions ZOO, Z, and Z2 respectively. Additionally, the electrode k constitutes the control electrode of an MOS transistor To whose region M' is the source and whose region ZO is the drain. As for the electrode k', it constitutes the control electrode of an MOS transistor Tio whose region ZO is the source and whose region ZOO is the drain. Because of the connection between k' and the contact aC, this transistor consequently has its control electrode connected to its drain.

It is apparent that the pair of electrodes k1-k'1, to which we now turn, constitute the control electrodes of respective parts T1-T11, of a double transistor structure whose region ZOO consitutes the source and whose region Z constitutes the drain. Because of the connection of the contact a with Wi, the transistor T', has its control electrode connected to its drain. Exactly the same is true of the pair k2~k'2 which constitute the control electrodes of the respective parts T2-To2 of a double transistor structure whose regions Z, and Z2 respectively constitute the source and the drain.The region Z2 also consitututes the source of the subsequent transistor structure, absolutely identical to the structures T1-T'1 and T2-T12 the beginning of the first electrode only of which, connected to the line P, has been represented in Fig. 1.

The circuit represented in Fig. 1 includes the injection or enabling stage as well as the first cell of a shift register. The injection stage is formed by the capacitor CO and the transistors To and Two, while the first cell of the register is formed of two identical stages in series, the first formed by the capacitor C, and the double MOS structure T,--T', and the second by the capacitor C2 and the double MOS structure T2-T12.

A A shift register according to the inventiqn will consequently comprise a plurality of cells similar to that in Fig. 1 and connected one after the other with their control electrodes connected to the bias line P and their two capacitors respectively connected to the lines X as regards the first stage and Y as regards the second.

Reference will now be made to Fig. 2 in which has been represented the equivalent diagram of a stage of the shift register according to the invention. Thus, this register comprises a capacitor Cn and a double transistor structure whose two components Tn and T'n have for control electrodes kn and kn respectively. This double structure is represented in the figure by two transistors connected by a dotted line which symbolizes the region common to the drain of Tn and the source of Tln.

The control electrode k of Tn is connected to the bias line P and its source is connected to the output of the preceding stage, formed by the drain of the second transistor T'n-1, of the latter. One of the plates of the capacitor Cn is connected to the line X or to the line Y according to whether the stage is the first or second, respectively, of the cell concerned.

The other plate of Cn is connected both to the drain and to the control electrode Wo of Tln.

The output of the stage, constituted by the drain of the transistor Tln is connected to the output of the following stage, formed by the source of the first transistor, Tn+1 of the latter.

With reference now to Figs. 1 and 2, as well as to the explanatory diagram in Fig. 3, the functioning of the shift register according to the invention can be described as follows.

With a view to simplification, the MOS structure threshold voltages will be taken to be 0.

The crystal being negatively biased in relation to the ground and the two lines X and Y being supplied by sinusoidal voltages in phase opposition +, (t) and +2 (t) respectively, if the transistor To is blocked, sinusoidal voltages va and vb (with peak-to-peak value Va and Vb respectively) appear on the regions Z, and Z2 at the points a and b respectively. The form of these two voltages is represented in the diagram in Fig. 3.If the transistor To is then controlled, between the instants to and t1, by application to its control electrode k (terminal E) of a pulse derived from the voltage +2 (t), electrons pass, in the interval to-ti, from the reference region M' to the regions ZO and, from there, via the transistor TZo, to the region ZOO. The capacitor CO is thus charged on the peak value of #2 (t). At the instant t1, the potential of the region ZOO in relation to M' is consequently practically 0.

The potential at the point a0 then assuming a a negative value in relation to M', the transistor Tio is blocked since its control electrode W is connected to the region ZOO. The electrons consequently pass to the region Z, via the MOS structure T1-T'1, and charge the capacitor C1 on the peak value of #1 (t). During the following half-period, that is to say, between the instants t2 and t3, the same technique is repeated for the transfer between the regions Z, and Z2 via the MOS structure T2-T12, of the charge packet 0 = C1 . , and so forth.

If the value of the reactance 1/#C1 = 1 /#C2 ( being the pulsatance of the oscillator) is far greater than the value of the differential resistance presented by the MOS structure of a stage, the current which has to be supplied by the oscillator for the #harge packet transfer is substantially sinusoidal and out of phase by almost 90 in relation to the phase voltages , (t) and 2 (t). The source-drain voltage of the MOS structure, which in this case also represents its control voltage, becomes very low for this transfer. The power which the oscillator has to supply is itself consequently very low.

Analysis, expressed in the same terms as those used previously for a shift register of the "IGFET bucket brigade" type, shows that the power to be supplied by the oscillator for the charge packet transfer is then PT = 1.8 VP vm.C.f.

Taking the same typical values as previously, a power of 0.45 W is obtained. This power was 2.2 W with the "IGFET bucket brigade" register. It is thus clear that the shift register according to the invention allows a considerable saving of power to be achieved.

As Fig. 3 shows, the voltage va which is established at the point a between the instants t, and t2 on transfer of the charge by the MOS structure T,-T', and then between the instants t2 and t3 on transfer by T2-T'2 is very low in relation to the voltage which is established when no transfer occurs. The same is true of the voltage vb at the point b between the instants t2 and t3, and then between the instants t3 and t4 when the charge passes through the following MOS structure. Because of this difference, the shift register according to the invention is particularly well suited to the realisation of frequency divider circuits.

Such a circuit is described in the patent application for ''Integrated Frequency Divider" filed today by the Applicant.

The shift register according to the invention can be realised according to the manufacturing technique known by the name of Si-gate.

A simpler technique called Al-gate can, of course, also be used. In this second instance, the structure of a stage is constituted by two MOS transistors in series. However, owing to the capacitance presented by the floating junction then forming the drain of the first and the source of the second.transistor, the register's performance runs the risk of being slightly diminished, in the sense essentially that the possible number of cells is lower than if the structure represented in Fig. 1 is used.

This is due to a certain loss of charge when it is transferred from one capacitor to another.

The register's injection stage, incidentally, instead of being constiuted by two transistors in series, can be identical to a stage of the register and consequently comprise only two n regions, M' and ZOO.

The shift register which has been described above is naturally capable of numerous variants remaining within the scope of the invention.

Claims

1. A shift register comprising a plurality of transistors and capacitors which are integrated in a semi-conductor substrate and form a plurality of cells connected one after the other, each cell comprising two identical stages connected in series and capable of being supplied by respective ones of two periodic signals in phase opposition, wherein each stage comprises an MOS transistor structure which has two principal electrodes forming respectively the input and output of the stage, and two control electrodes, one of which is connected, in use, to a bias source and the other of which is connected to the output electrode, and a capacitor, one plate of which is connected to the said output electrode and the other plate of which receives, in use, one of the said periodic signals, depending on the position of the stage in the register.

2. A shift register according to claim 1, wherein the said transistor structure includes a MOS transistor with two control electrodes.

3. A shift register according to claim 1, wherein the said transistor structure includes two MOS transistors connected in series.

4. A shift register according to claim 2, wherein the transistor structure and the capacitor of one stage are formed by first and second semi-conductor regions of a type opposite to that of the substrate in which they are integrated, a first insulated conductor layer beginning above the first region and stopping substantially halfway between the first and second region, a second insulated conductor layer beginning substantially halfway between the first and second region and stopping above the second region, a third conductor layer in contact with the said second region and connected to the second conductor layer, and a fourth insulated conductor layer disposed opposite the second region, the two semi-conductor regions forming the principal electrodes of the transistor structure, the first and second conductor layers of which form the respective control electrodes, and the fourther conductor layer forming one plate of the capacitor whose other plate is formed by the said second region.

5. A shift register according to claim 4, wherein the said first and second semi-conductor regions also respectively form the second semiconductor region of the preceding stage and the first semi-conductor region of the following stage.