CH501980A - Monolithische, integrierte Halbleiteranordnung - Google Patents
Monolithische, integrierte HalbleiteranordnungInfo
- Publication number
- CH501980A CH501980A CH22870A CH22870A CH501980A CH 501980 A CH501980 A CH 501980A CH 22870 A CH22870 A CH 22870A CH 22870 A CH22870 A CH 22870A CH 501980 A CH501980 A CH 501980A
- Authority
- CH
- Switzerland
- Prior art keywords
- monolithic
- semiconductor device
- integrated semiconductor
- integrated
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/415—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
- H10B99/10—Memory cells having a cross-point geometry
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
- H10D89/311—Design considerations for internal polarisation in bipolar devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Electronic Switches (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US79147769A | 1969-01-15 | 1969-01-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH501980A true CH501980A (de) | 1971-01-15 |
Family
ID=25153857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH22870A CH501980A (de) | 1969-01-15 | 1970-01-09 | Monolithische, integrierte Halbleiteranordnung |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3621302A (enExample) |
| CA (1) | CA936597A (enExample) |
| CH (1) | CH501980A (enExample) |
| DE (1) | DE2001530C3 (enExample) |
| FR (1) | FR2028333A1 (enExample) |
| GB (1) | GB1234709A (enExample) |
| NL (1) | NL7000547A (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3732440A (en) * | 1971-12-23 | 1973-05-08 | Ibm | Address decoder latch |
| NL163338C (nl) * | 1972-03-25 | 1980-08-15 | Philips Nv | Elektronische schakeling. |
| US3870901A (en) * | 1973-12-10 | 1975-03-11 | Gen Instrument Corp | Method and apparatus for maintaining the charge on a storage node of a mos circuit |
| US4151488A (en) * | 1978-02-22 | 1979-04-24 | Raytheon Company | Pulsed power supply |
| FR2443118A1 (fr) * | 1978-11-30 | 1980-06-27 | Ibm France | Dispositif pour l'alimentation des memoires monolithiques |
| FR2445642A1 (fr) * | 1978-12-29 | 1980-07-25 | Radiotechnique Compelec | Agencement de securite en cas de chute d'une tension d'alimentation continue |
| JPS56143587A (en) * | 1980-03-26 | 1981-11-09 | Fujitsu Ltd | Static type memory circuit |
| JPH0693484B2 (ja) * | 1989-11-10 | 1994-11-16 | 株式会社東芝 | 半導体集積回路 |
| JP2723338B2 (ja) * | 1990-04-21 | 1998-03-09 | 株式会社東芝 | 半導体メモリ装置 |
| US5321658A (en) * | 1990-05-31 | 1994-06-14 | Oki Electric Industry Co., Ltd. | Semiconductor memory device being coupled by auxiliary power lines to a main power line |
| US5701143A (en) * | 1995-01-31 | 1997-12-23 | Cirrus Logic, Inc. | Circuits, systems and methods for improving row select speed in a row select memory device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3226574A (en) * | 1963-09-20 | 1965-12-28 | Martin Marietta Corp | Power saving storage circuit employing controllable power source |
| DE1524873B2 (de) * | 1967-10-05 | 1970-12-23 | Ibm Deutschland | Monolithische integrierte Speicherzelle mit kleiner Ruheleistung |
-
1969
- 1969-01-15 US US791477*A patent/US3621302A/en not_active Expired - Lifetime
- 1969-12-04 FR FR6941866A patent/FR2028333A1/fr not_active Withdrawn
- 1969-12-15 GB GB60960/69A patent/GB1234709A/en not_active Expired
- 1969-12-15 CA CA069790A patent/CA936597A/en not_active Expired
-
1970
- 1970-01-09 CH CH22870A patent/CH501980A/de not_active IP Right Cessation
- 1970-01-14 NL NL7000547A patent/NL7000547A/xx not_active Application Discontinuation
- 1970-01-14 DE DE2001530A patent/DE2001530C3/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2001530A1 (de) | 1970-07-30 |
| US3621302A (en) | 1971-11-16 |
| GB1234709A (en) | 1971-06-09 |
| FR2028333A1 (enExample) | 1970-10-09 |
| DE2001530C3 (de) | 1974-03-07 |
| CA936597A (en) | 1973-11-06 |
| NL7000547A (enExample) | 1970-07-17 |
| DE2001530B2 (de) | 1973-07-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |