CH470760A - Verfahren zur Herstellung einer Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung

Info

Publication number
CH470760A
CH470760A CH1314566A CH1314566A CH470760A CH 470760 A CH470760 A CH 470760A CH 1314566 A CH1314566 A CH 1314566A CH 1314566 A CH1314566 A CH 1314566A CH 470760 A CH470760 A CH 470760A
Authority
CH
Switzerland
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
CH1314566A
Other languages
German (de)
English (en)
Inventor
John Dean Ronald
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of CH470760A publication Critical patent/CH470760A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
CH1314566A 1965-09-13 1966-09-12 Verfahren zur Herstellung einer Halbleitervorrichtung CH470760A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB38976/65A GB1108778A (en) 1965-09-13 1965-09-13 Improvements in and relating to methods of manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
CH470760A true CH470760A (de) 1969-03-31

Family

ID=10406859

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1314566A CH470760A (de) 1965-09-13 1966-09-12 Verfahren zur Herstellung einer Halbleitervorrichtung

Country Status (7)

Country Link
US (1) US3435514A (enExample)
AT (1) AT271570B (enExample)
BE (1) BE686760A (enExample)
CH (1) CH470760A (enExample)
ES (1) ES331088A1 (enExample)
GB (1) GB1108778A (enExample)
NL (1) NL6612709A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996003771A1 (en) * 1994-07-25 1996-02-08 Micro Components & Systems Ltd. Method of manufacturing a composite structure for use in electronic devices and structure, manufactured by said method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3529759A (en) * 1967-06-15 1970-09-22 Bell Telephone Labor Inc Apparatus for bonding a beam-lead device to a substrate
JPS59155950A (ja) * 1983-02-25 1984-09-05 Shinko Electric Ind Co Ltd 半導体装置用セラミックパッケージ
FR2704094B1 (fr) * 1993-04-13 1995-07-07 Sgs Thomson Microelectronics Réseau de diodes monolithique.

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2744308A (en) * 1950-11-17 1956-05-08 Bell Telephone Labor Inc Semi-conductor translating device and method of manufacture
US3169892A (en) * 1959-04-08 1965-02-16 Jerome H Lemelson Method of making a multi-layer electrical circuit
GB1015909A (en) * 1963-12-30 1966-01-05 Gen Micro Electronics Inc Method of and product for packaging electronic devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996003771A1 (en) * 1994-07-25 1996-02-08 Micro Components & Systems Ltd. Method of manufacturing a composite structure for use in electronic devices and structure, manufactured by said method
US5661341A (en) * 1994-07-25 1997-08-26 Microcomponents And Systems Ltd. Method of manufacturing a composite structure for use in electronic devices and structure, manufactured by said method

Also Published As

Publication number Publication date
GB1108778A (en) 1968-04-03
ES331088A1 (es) 1967-07-01
BE686760A (enExample) 1967-03-13
NL6612709A (enExample) 1967-03-14
AT271570B (de) 1969-06-10
DE1564443A1 (de) 1970-05-27
DE1564443B2 (de) 1975-06-26
US3435514A (en) 1969-04-01

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Legal Events

Date Code Title Description
PL Patent ceased