AT329116B - Verfahren zur herstellung einer halbleiteranordnung - Google Patents
Verfahren zur herstellung einer halbleiteranordnungInfo
- Publication number
- AT329116B AT329116B AT594071A AT594071A AT329116B AT 329116 B AT329116 B AT 329116B AT 594071 A AT594071 A AT 594071A AT 594071 A AT594071 A AT 594071A AT 329116 B AT329116 B AT 329116B
- Authority
- AT
- Austria
- Prior art keywords
- manufacturing
- semiconductor arrangement
- semiconductor
- arrangement
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/043—Dual dielectric
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/113—Nitrides of boron or aluminum or gallium
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/114—Nitrides of silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NLAANVRAGE7010207,A NL169121C (nl) | 1970-07-10 | 1970-07-10 | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon. |
Publications (2)
Publication Number | Publication Date |
---|---|
ATA594071A ATA594071A (de) | 1975-07-15 |
AT329116B true AT329116B (de) | 1976-04-26 |
Family
ID=19810547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT594071A AT329116B (de) | 1970-07-10 | 1971-07-08 | Verfahren zur herstellung einer halbleiteranordnung |
Country Status (12)
Country | Link |
---|---|
US (1) | US3755014A (de) |
JP (1) | JPS517551B1 (de) |
AT (1) | AT329116B (de) |
BE (1) | BE769732A (de) |
CA (1) | CA938032A (de) |
CH (1) | CH528821A (de) |
DE (1) | DE2133979C3 (de) |
ES (1) | ES393038A1 (de) |
FR (1) | FR2098322B1 (de) |
GB (1) | GB1352779A (de) |
NL (1) | NL169121C (de) |
SE (1) | SE367512B (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1388926A (en) * | 1972-03-04 | 1975-03-26 | Ferranti Ltd | Manufacture of silicon semiconductor devices |
NL7204741A (de) * | 1972-04-08 | 1973-10-10 | ||
US3999213A (en) * | 1972-04-14 | 1976-12-21 | U.S. Philips Corporation | Semiconductor device and method of manufacturing the device |
US3810796A (en) * | 1972-08-31 | 1974-05-14 | Texas Instruments Inc | Method of forming dielectrically isolated silicon diode array vidicon target |
JPS5228550B2 (de) * | 1972-10-04 | 1977-07-27 | ||
NL161301C (nl) * | 1972-12-29 | 1980-01-15 | Philips Nv | Halfgeleiderinrichting en werkwijze voor de vervaar- diging daarvan. |
JPS5242634B2 (de) * | 1973-09-03 | 1977-10-25 | ||
JPS604590B2 (ja) * | 1973-10-30 | 1985-02-05 | 三菱電機株式会社 | 半導体装置の製造方法 |
DE2409910C3 (de) * | 1974-03-01 | 1979-03-15 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Herstellen einer Halbleiteranordnung |
NL7506594A (nl) * | 1975-06-04 | 1976-12-07 | Philips Nv | Werkwijze voor het vervaardigen van een halfge- leiderinrichting en halfgeleiderinrichting ver- vaardigd met behulp van de werkwijze. |
FR2341201A1 (fr) * | 1976-02-16 | 1977-09-09 | Radiotechnique Compelec | Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu |
JPS6028397B2 (ja) * | 1978-10-26 | 1985-07-04 | 株式会社東芝 | 半導体装置の製造方法 |
US4381956A (en) * | 1981-04-06 | 1983-05-03 | Motorola, Inc. | Self-aligned buried channel fabrication process |
JPH01214136A (ja) * | 1988-02-23 | 1989-08-28 | Mitsubishi Electric Corp | 半導体集積装置 |
US6693308B2 (en) * | 2002-02-22 | 2004-02-17 | Semisouth Laboratories, Llc | Power SiC devices having raised guard rings |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA826343A (en) * | 1969-10-28 | Kooi Else | Methods of producing a semiconductor device and a semiconductor device produced by said method | |
US3386865A (en) * | 1965-05-10 | 1968-06-04 | Ibm | Process of making planar semiconductor devices isolated by encapsulating oxide filled channels |
NL152707B (nl) * | 1967-06-08 | 1977-03-15 | Philips Nv | Halfgeleiderinrichting bevattende een veldeffecttransistor van het type met geisoleerde poortelektrode en werkwijze ter vervaardiging daarvan. |
-
1970
- 1970-07-10 NL NLAANVRAGE7010207,A patent/NL169121C/xx not_active IP Right Cessation
-
1971
- 1971-07-07 GB GB3184271A patent/GB1352779A/en not_active Expired
- 1971-07-07 CH CH1001171A patent/CH528821A/de not_active IP Right Cessation
- 1971-07-07 CA CA117586A patent/CA938032A/en not_active Expired
- 1971-07-07 SE SE08802/71A patent/SE367512B/xx unknown
- 1971-07-08 BE BE769732A patent/BE769732A/xx unknown
- 1971-07-08 AT AT594071A patent/AT329116B/de not_active IP Right Cessation
- 1971-07-08 US US00160652A patent/US3755014A/en not_active Expired - Lifetime
- 1971-07-08 ES ES393038A patent/ES393038A1/es not_active Expired
- 1971-07-08 DE DE2133979A patent/DE2133979C3/de not_active Expired
- 1971-07-09 FR FR7125296A patent/FR2098322B1/fr not_active Expired
- 1971-07-10 JP JP46050735A patent/JPS517551B1/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPS472520A (de) | 1972-02-07 |
ES393038A1 (es) | 1973-08-16 |
ATA594071A (de) | 1975-07-15 |
GB1352779A (en) | 1974-05-08 |
DE2133979C3 (de) | 1979-08-23 |
DE2133979A1 (de) | 1972-01-13 |
JPS517551B1 (de) | 1976-03-09 |
FR2098322B1 (de) | 1974-10-11 |
FR2098322A1 (de) | 1972-03-10 |
SE367512B (de) | 1974-05-27 |
NL7010207A (de) | 1972-01-12 |
NL169121C (nl) | 1982-06-01 |
CH528821A (de) | 1972-09-30 |
DE2133979B2 (de) | 1978-12-21 |
NL169121B (nl) | 1982-01-04 |
US3755014A (en) | 1973-08-28 |
CA938032A (en) | 1973-12-04 |
BE769732A (fr) | 1972-01-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ELJ | Ceased due to non-payment of the annual fee |