CA2196268C - Package - Google Patents

Package Download PDF

Info

Publication number
CA2196268C
CA2196268C CA002196268A CA2196268A CA2196268C CA 2196268 C CA2196268 C CA 2196268C CA 002196268 A CA002196268 A CA 002196268A CA 2196268 A CA2196268 A CA 2196268A CA 2196268 C CA2196268 C CA 2196268C
Authority
CA
Canada
Prior art keywords
lead frame
bank
chip
package
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002196268A
Other languages
French (fr)
Other versions
CA2196268A1 (en
Inventor
Seiji Ichikawa
Tomoaki Hirokawa
Tomoaki Kimura
Junichi Tanaka
Taku Sato
Satoshi Murata
Tsutomu Kubota
Takeo Ogihara
Kenji Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2196268A1 publication Critical patent/CA2196268A1/en
Application granted granted Critical
Publication of CA2196268C publication Critical patent/CA2196268C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package of the present invention comprises a base molded integrally with a lead frame by resin, a chip mounted on the lead frame, and a cap made of resin, which covers the chip and is fixed to the base.
The base includes a substrate portion sealing the lead frame therein, a frame-shaped bank portion formed at a periphery of an upper surface of said substrate portion, the bank portion having said lead frame interposed between it and the substrate portion, and an anchor portion formed at a portion of the lead frame interposed between the substrate portion and the bank portion. The chip is mounted on a region of the lead frame surrounded by the bank portion. The cap is fixed to the bank portion.

Description

219b2b8 PACRAGE
BACRGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a package, more -particularly to a mold package which seals a chip mounting an ultra high frequency semiconductor, an optical element, a surfac~elastic wave element, a resonator, or the like.
2. Description of the Related Art:
In an ultra high frequency device, when a size of its package becomes larger, an inductance component of a lead becomes larger, whereby a loss in a high frequency becomes larger.-==Therefore, the ultra high frequency device must be housed in a package which is as small as about 2 mm diameter. Furthermore, the ultra high frequency device has been heretofore incor-porated in a ceramic hollow package. However, the ceramic package is high in cost so that the ultra high frequency device has a tendency to be incorporated in a resin mold package.
Since resin has a high dielectric constant, a parasitic capacitance becomes high when the whole of the device is sealed by resin. A high frequency gain of the device can not be obtained. To solve such problem, a resin mold package in which a space is I-_ '~ ,~ 2196268 provided on a surface of the device has been proposed.
For example, in a gazette No. W094/17552, disclosed is a high frequency plastic package having a structure that a semiconductor chip is mounted on a lead frame, a substrate portion made of resin mounting the lead frame on its surface is covered with a plastic cap, whereby the semiconductor chip is sealed.
Furthermore, in Japanese Patent Application Laid Open No. Heisei 2-25057, disclosed is a method of manufacturing a semiconductor device wherein after molding a resin case having an opening at its upper portion integrally with a lead frame having an inner lead portion at its inner bottom, the inner lead portion and a semiconductor chip are connected each to other, and a cover for sealing the semiconductor chip is adhered to the resin case.
Furthermore, in Japanese Patent Application Laid Open No. Heisei 5-291319, disclosed is a semiconductor device wherein a pad of a semiconductor chip and a metal foil are connected through a connection project-ing electrode, the metal foil being formed on a flexible film substrate, a frame-shaped dam pattern is formed either outside the projecting electrode or inside it, and by interposing the semiconductor chip and the flexible film substrate using a resin sheet for sealing, both of the chip and the substrate are -_ 2 _ '~ 219628 integrally fixed to each other. In Japanese Utility Model Application Laid Open No. Showa 62-135441, disclosed is a flip chip mounting structure wherein a flip chip having a solder bump formed thereon is connected onto a substrate provided with a plurality of electrodes thereon, and a space having a height equal to the solder bump is formed between the substrate and the flip chip by dropping resin onto the flip chip from -a direction above the flip chip.
However, in the high frequency plastic package disclosed in the W094/17552 gazette, since a bending working for the lead frame is conducted after sealing the plastic cap, there are problems that due to stress applied at the lead frame bending working, the lead frame moves over the mold, the plastic cap is cracked, or a adhered portion is peeled off whereby the plastic cap is detached_ On the other hand, in the manufacturing method of the semiconductor device disclosed in the Japanese 2p Patent Application Laid Open No. Heisei 2-25057, an outer periphery of the opening serves as a frame por-tion, and the lead frame is held between a base portion and a frame portion. Therefore, the above-described _ problems hardly occur. However, in general, electronic parts are initially mounted at a specified position of a printed circuit board and the like by a handler of a r mounting machine and is soldered to the printed circuit board. Further, the printed board is partially sealed with a sealing case. Or, the printed circuit board is attached to a case of a body.
During these processes, a portion of the handler, the sealing case, or a driver sometimes touches inad-vertently the package which has been already mounted on the substrate. In the case of comparatively large package, it is possible to form the frame so as to have a thick thickness, so that the package is never broken when the handler and the like touches the package.
However, since in a case of packages for a ultra high frequency device, its diameter is about 2 mm, a thickness of the frame is as small as about 0.5 mm.
Therefore, with an application of a slight shearing stress in a lateral direction to the package, there is a possibility of breakdown of the package.
In the semiconductor device disclosed in the Japanese Patent Application Laid Open No. Heisei 5-291319, since the flexible film or the resin sheet is used as a main body, there is a problem that the package itself has a poor mechanical strength. Furthermore, the package is distorted by an application of pressure at sealing, and there is a possibility that resin flows into the inside of the package from a small space of the dam pattern, thereby reducing reliability of the device. In the mounting structure disclosed in the Japanese Utility Model Application Laid Open No. howa 62-135441, the dropped resin spreads into the periphery of the semiconductor chip, so that a problem of flowing of the resin still remains. Furthermore, unless optimization for a viscosity of the resin and for a space between the substrate and the semiconductor chip are done, the space between the substrate and the semiconductor chip is not always formed.
SUMMARY OF THE INVENTION
The present invention is to provide a package which has an excellent high frequency characteristic and is capable of bearing with automatic mounting, even when adopting a resin for the package.
To achieve the foregoing object, a package of the present invention comprises:
a base including a lead frame, a substrate portion sealing said lead frame therein, a frame-shaped bank portion formed at an outer periphery of an upper sur-face of said substrate portion, said bank portion having said lead frame interposed between it and the substrate portion, and an anchor portion formed in a portion of said lead frame interposed between said substrate portion and said bank portion, said substrate portion and said bank portion being molded integrally with said lead frame by resin;
a chip electrically connected to said lead frame and mounted on a region of said lead frame on said base, said region being surrounded by said bank portion; and a cap made of resin covering the said chip, said cap being fixed onto said bank portion and having a recess therein which cooperates with the base to form a cavity for housing the chip.
As described above, the chip is mounted on the region of the lead frame surrounded by the bank portion of the base made of resin, and the cap made of resin is fixed to the bank portion. Thus, obtained is a resin mold hollow package in which the chip is sealed in a hollow portion formed by the base and the cap. In such package, an anchor portion is formed at a position of the lead frame interposed between the substrate portion and the bank portion, whereby intensity of the package is enhanced in spite of the resin mold hollow package.
The anchor portion may be an anchor hole formed in the lead frame, which connects the substrate portion to the bank portion. Furthermore, a blade portion, jagged stripes, or a nail portion is formed in the lead frame in addition to the anchor hole, whereby pulling-up strength of the lead frame is enhanced.
Furthermore, a package of the present invention comprises:
a base including a lead frame, a substrate portion sealing said lead frame therein, and a framed-shaped bank portion formed on an upper surface of said substrate portion, said bank portion having said lead frame interposed between it and said substrate portion, and said substrate portion and said bank portion being formed integrally with said lead frame by resin;
a chip electrically connected to said lead frame and mounted on a region of said lead frame on said base, said region being surrounded by said bank portion; and a cap made of resin covering the said chip, said cap being fixed onto said bank portion and having a recess therein which cooperates with the base to form a cavity for housing the chip, wherein said bank portion is arranged inside an inner wall of said cap and said cap is fixed to an edge of said substrate portion and an outer wall surface of said bank portion.
Also with the package constituted as described above, obtained is a resin mold hollow package in which the chip is sealed in a hollow portion between the base and the cap. In addition, since the cap is fixed to the outer periphery of the substrate portion and the outer wall surface of the bank portion, the intensity of the package itself is reinforced by the bank portion, and the fixing intensity is increased.
Moreover, when the cap is fixed to the base, the bank portion serves as a guide for the cap, so that the positioning accuracy is increased.
comprises:
Furthermore, a package of the present invention a base including a lead frame and a substrate portion sealing said lead frame therein, said substrate portion being formed integrally with said lead frame;
a chip mounted on a portion of said lead frame disposed on said base, said chip being electrically connected to said lead frame; and a cap made of resin fixed to said base, said cap covering said chip, and having a recess therein which cooperates with the base to form a cavity for housing the chip;
wherein said lead frame is drawn out from a side surface of said substrate portion and has a chip mounting portion for mounting said chip and a bonding portion electrically connected to said chip, said chip mounting portion and said bonding portion are bent so as to be exposed to a surface of said substrate portion.
Also in the package constituted as described above, obtained is a resin mold hollow package in which the chip is sealed in a hollow portion between the base and the cap.
Moreover, the lead frame is held in the substrate portion in the state where it is bent to display a crank shape, whereby the pulling-up strength of the lead frame increases.
Particularly, by making the upper surface of the base flat, removal of resin ' '~ 219b2b8 flashes occurring in the chip mounting portion and boding portion of the lead frame at the time of molding the base are facilitated.
Furthermore, a package of the present invention comprises:
a base including a lead frame, a substrate portion sealing said lead frame therein, and a frame-shaped bank portion formed at a periphery on an upper surface of said substrate portion, which interposes said lead frame with said substrate portion, and said substrate portion and said bank portion being formed integrally with said lead frame by resin; and a chip mounted on a region, surrounded by said bank portion, in said lead frame on said base, said chip being electrically connected to said lead frame, wherein said chip having a plurality of projection electrodes on its electrode formation surface facing said lead frame is connected to said lead frame and said chip is sealed with dropped resin, and a space is provided between said chip and said substrate portion.
In the package constituted as described above, since the lead frame is connected to the chip having the electrode formation surface provided with the projection electrodes facing the lead frame, obtained is a resin mold hollow package in which a space is formed between the electrode formation surface of the _ g _ .
__ ~196~6~
chip and the lead frame. In addition, since the inside of the bank portion is filled with a sealing resin, the intensity of the package itself increases.
BRIEF DESCRIPTION OF THE DRAWIGNS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which;
Fig. 1(a) is a plan view showing a package of a first embodiment of the present invention before seal-ing with a cap;
Fig. 1(b) is a sectional view taken along the line A-A of Fig. 1(a) showing the package of the first embodiment of the present invention after sealing with the cap;
Figs. 2(a) to 2(e) show a manufacturing method of the package shown in Figs. 1(a) and 1(b);
Fig. 3(a) is a plan view of a package of a second embodiment of the present invention before sealing with a cap;
Fig. 3(b) is a sectional view taken along the line B-B of Fig. 3(a) showing the package of the second embodiment of the present invention after sealing with the cap;
Figs. 4(a) to 4(c) show a manufacturing method of ~19626~
the package show in Figs. 3(a) and 3(b);
Fig. 5(a} is a plan view of a package of a third embodiment of the present invention before sealing with a cap;
Fig. 5(b) is a sectional view taken along the line C-C of Fig. 5(a) showing the package of the third embodiment of the present invention after sealing with the cap;
Fig. 6 is a schematic view showing a method for -forming a lead frame of the package shown in Figs. 5(a) and 5(b};
Fig. 7(a) is a plan view a plan view showing a package of a fourth embodiment of the present invention before sealing with a caps Fig. 7(b} is a sectional view taken along the line D-D of Fig. 7(a) showing the package of the fourth embodiment of the present invention after sealing with the cap;
Fig. 8(a) is a plan view a plan view showing a package of a fifth embodiment of the present invention before sealing with a cap;
Fig. 8(b) is a sectional view taken along the line =
E-E of Fig. 8(a) showing the package of the fifth embodiment of the present invention after sealing with the cap;
Fig. 9(a) is a plan view a plan view showing a package of a sixth embodiment of the present invention before sealing with a cap;
Fig. 9(b) is a sectional view taken along the line F-F of Fig. 9(a) showing the package of the sixth embodiment of the present invention after sealing with the cap;
Fig. 10 is a figure showing dimensions of main -parts of the lead frame shown in Figs. 9(a) and 9(b);
Fig. 11(a) is a plan view showing a package of a seventh embodiment of the present invention before dropping resin for sealing thereon;
Fig. 11(b) is a sectional view showing the package of the seventh embodiment of the present invention after sealing by resin;
Figs. 12(a) to 12(c) are figures showing a manufacturing method of the package shown in Figs. 11(a) and 11(b);
Fig. 13(a) is a plan view showing a package of a eighth embodiment of the present invention before dropping resin for sealing thereon;
Fig. 13(b) is a sectional view showing the package of the eighth embodiment of the present invention after sealing by resin;
Figs. 14(a) to 14(c) are figures showing a manufacturing method of the package shown in Figs.
13(a) and 13(b);

Fig. 15 is a graph showing a comparison of break-ing shearing force of the package of the first embodi-ment with those of other embodiments; and Fig. 16 is a sectional view of a conventional semiconductor package in which a base is cpnstituted by integrating resin with a lead bent by a bending working in a crank shape.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of the present invention will be described with reference to the accompanying drawings.
( First Embodiment ) A package of the first embodiment of the present invention will be described with reference to Figs. 1(a) and 1( b ).
Referring to Figs. 1(a) and 1(b), the package of this embodiment consists of a base 11 including a lead frame 12, a chip 14 mounted on the base 11, and a cap 15 covering the chip 14, which is fixed to the base 11.
The base 11 consists of the lead frame 12, a substrate portion 13a sealing the lead frame 12, and a frame-shaped bank portion 13b interposing the lead frame 12 at a periphery of an upper surface of the base portion 13a, the bank portion 13b having the same outer shape as that of the base portion 13a. The base por-tion 13a and the bank portion 13b are made of resin, and they are formed integrally with the lead frame 12 by a metallic mold (not shown). Thus, the lead frame 12 is interposed between the base portion 13a and the bank portion 13b to be held. Anchor holes 12a for connecting the base portion 13a to the bank portion 13b are formed at the positions corresponding to the inner lead of the lead frame 12 between the base portion 13a and the bank portion 13b. Resin is filled in the anchor holes 12a by molding with the metallic mold.
Cu alloy or 42 alloy (Ni-Fe alloy containing 42%N:) or the like is used as a material of the lead frame 12.
Moreover, resin of epoxy type, liquid polymer (LCP), or polyphenylene sulfide (PPS) is used as a material of the resin portion of the base 11, or a material of the base portion 13a and the bank portion 13b.
The chip 14 is mounted on the lead frame 12 at a region surrounded by the bank portion 13b and is connected to the lead frame 12 electrically by a bonding line 17. The cap 15 is molded using the same kind of resin as that of the base 11. The cap 15 is adhered to the upper surface of the bank portion 13b with an adhesive agent made of epoxy type resin or phenol type resin. Thus, obtained is a resin mold package having a hollow portion sealing the chip 14, the hollow portion being formed by the base 11 and the cap 15. Therefore, this package has an excellent high frequency characteristic although a resin package is employed. It should be noted that the resin portion of the base 11 may be formed of different resin from that of the cap 15. For example, the cap 15 may be formed of transparent resin when an optical device is used as the chip.
Dimensions of each portion of the package of this embodiment will be described below. In the resin portion of the base 11, a thickness of the substrate portion 13a is 0.3 mm, a width of the bank portion 13b is 0.35 mm, and a height thereof is 0.2 mm. In the lead frame 12, a width is 0.5 mm, a thickness is 0.12 mm, and a diameter of the anchor hole 12(a) is 0.2 mm. In the cap 15, a diameter is 1.9 mm, a height is 0.5 mm, a resin thickness is 0.3 mm.
Next, an example of a manufacturing method of the package will be described with reference to Figs. 2(a) to 2(e).
( a ) The lead frame 12 is formed in a specified shape by press working or etching processing ( Fig.
2(a) ).
( b ) The lead frame 12 is disposed within a cavity formed by the mold ( not shown ). Resin is injected into the cavity. Thus, the base 11 is formed which holds the lead frame 12 by its substrate portion 13a and bank portion.l3b ( Fig. 2(b) ). At the time~of ' . ' ._ ~19~268 injection of the resin to the cavity, the anchor hole 12a of the lead frame 12 is also filled with the resin.
Also in this portion, the substrate 13a and the bank portion 13b are integrated with each other.
( c ) The chip 14 is mounted on the lead frame 12.
The lead frame 12 and the chip 14 are connected by the bonding line 17 ( Fig. 2(c) ).
( d ) Adhesive agent 16 is coated on the adhesion surface of the bank portion 13b where the cap 15 is adhered thereto, whereby the cap 15 is adhered to the upper surface of the bank portion 13b ( Fig. 2(d) ).
As a result, the chip 14 is sealed within the hollow portion formed by the base 11 and the cap 15.
( a ) The periphery portion of the lead frame 12 is cut, and the portion corresponding to the outer lead o~ the lead frame 12 is subjected to bending working ( Fig. 2(e) ).
The package is completed through the above-described steps.
Here, in the package of this embodiment, under the situation where the lead frame 12 was soldered onto the printed circuit board, a shearing force in a lateral direction was applied to the uppermost portion of the cap 15 by means of a push-pull gauge. The shearing force applied when the package was broken was measured.
The number of test samples was 20, and the trend of the ~i ~19626~
frequency distribution of the shearing force in this embodiment is illustrated in Fig. 15. For comparison, similar tests were conducted for the conventional package using the cap formed of ceramic ( Comparing Example 1 ) and for the package constituted in the similar manner to this embodiment except that no anchor hole is formed in the lead frame ( Comparing Example 2 ).
The results are illustrated in Fig. 15 together with that of this embodiment.
As a result of the experiments, in the package of this embodiment, a breakdown of the package occurred at the bank portion, and the average of the shearing force at the time of the breakdown of the bank portion was 3.7 kg. Moreover, in the Comparing Example 1, a break-down occurred between an adhesive for adhering the cap and the lead frame, and the average of the shearing force at the time of the breakdown of that portion was 5 kg. In the Comparison Example 2, a breakdown oc-curred at the bank portion, and the average of the shearing force at the time of the breakdown of the bank portion was 2.2 kg. From the above results, it was found that the package has a strength nearly equal to that of the ceramic package by means of the anchor hole 12a even though that package is a resin mold hollow type package.
The formation of the anchor hole in the lead frame -~ 17 -is disclosed also in Japanese Patent Application Laid Open No. Heisei 5-226548 and Heisei 7-122692.
Specifically, in the Japanese Patent Application Laind Open No. Heisei 5-226548, disclosed is the lead -frame formed in the following manner. A hole having a semi-circle shaped section is formed in the surface of -the inner lead portion by etching technique. Thereaf- .z ter, a hole having a semi-circle shaped section is formed also in the rear surface of the inner lead portion. Both holes are connected thereby forming the anchor hole. However, this anchor hole serves to absorb the mechanical shock produced at the step for cutting the lead frame and the step for bending it, and also the package using the lead frame is not a hollow type one. Therefore, there is no necessity to appre-bend the breakdown of the package due to contacting of the handler of the mounting machine with the packacre.
Moreover, in the Japanese Patent Application Laid Open No. Heisei 7-122692, disclosed is a semiconductor device having a structure that a lead frame is inter-posed between a base portion and a sealing portion constituting an envelop. An anchor hole is formed at the portion of the lead frame between the base portion and the sealing portion. Adhesive of glass type is filled in the anchor hole. In this situation, the lead frame is adhered to the base portion and the sealing ._ , __ ' portion. Moreover, the base portion and the sealing portion are made of ceramic. Thus, since the base portion and the sealing portion are made of ceramic, the lead frame is constructed so as to be interposed between the base portion and the sealing portion. Even though this structure were constructed by mold resin, peeling off of the adhered portion due to the stress applied at the lead frame bending working may happen so that floating of the lead frame from the adhered portion or detachment of the sealing portion occur, like the case of the foregoing W094/17552 gazette.
Accordingly, this structure is effective on the semiconductor package in which a large area is available for adhesion. However, this structure is not suitable for a small sized package for use in an ultra high frequency device.
( Second Embodiment ) A package of a second embodiment of the present invention will be described with reference to Figs. 3(a) and 3(b).
In this embodiment, a blade portion 22b protruding in a thickness direction of the lead frame 22 is formed at the position between the substrate portion 23a and the bank portion 23b, in addition to the anchor hole 22a. The blade portion 22b is made by bending the both side portions of the lead frame 22 corresponding to the foregoing position toward the bank portion 23b. In this embodiment, the length of the blade portion 22b shall be 0.15 mm, and the height thereof shall be 0.1 mm. Constitutions and materials of other portions of the package are the same as those of the first embodi-ment and the description for them are omitted.
An example of a formation method of the blade portion 22b will be described with reference to Figs. 4(a) and 4(c). First, the lead frame 33 is formed in a specified shape by press working or etching processing.
At this time, the portion which serves as the blade portion 22b is made so as to be wider than other portions, as shown in Fig. 4(a).
Subsequently, the wider portion is bent by press working. Thus, as shown in Figs. 4(b) and 4(c), the blade portion 22b is formed in both sides of the lead frame 2 2 .
As described above, the formation of the blade portion 22b in the lead frame 22 increases pulling-up strength of the lead frame 22. Particularly, the protrusion of the blade portion 22b into the bank portion 23b makes the contact area of the lead frame 22 with the bank portion 23b larger, whereby a strength against a shearing force applied to the lead frame is further increased. In the same manner as the first embodiment, the shearing force when the package is broken was measured. The value of the shearing force was 4.8 kg. It was found that the a resin mold hollow package having a strength closer to that of a ceramic package was obta~.ned. It should be noted that when the blade portion 22b having a protrusion in a direction of the substrate portion 23a is formed, its pulling-up strength increases compared to the first embodiment although the strength against the shearing force is the same as the first embodiment.
{ Third Embodiment A package of a third embodiment of the present invention will be described with reference to Figs. 5(a) and 5(b).
In the package of the third embodiment, the jagged stripes 32b are formed at the portion of the lead frame 32 interposed between the substrate portion 33a and the bank portion 33b, in addition to the anchor hole 32a.
The jagged stripes 32b are constituted of tops and bottoms along the width direction of the lead frame 32, which are arranged alternately in the longitudinal direction of the lead frame 32. For a forming method of the jagged stripes 32b, there has been a method wherein after the formation of the lead frame 32 by press working in a specified shape in the same manner as the first embodiment, as shown in Fig. 6, the lead :., frame 32 is stamped by a punch 38 having the V-shaped top end. In this case, the length of the lead frame 32.
becomes shorter because of the formation of the jagged -stripes 32b. Therefore, the length of the lead frame must be determined considering this shortened amount -when forming the lead frame 32 by the press working and so on. In this embodiment, the length of the jagged stripes 32b was set to be 0.15 mm, and the height of the jagged stripes 32b from the surface of the lead -frame 32 was set to be 0.1 mm. Other constitutions and the materials of the lead frame 32 are the same as those of the first embodiment. Therefore, the descrip- -tions for them are omitted.
As described above, the formation of the jagged stripes 32b enhances the pulling-up strength of the lead frame 32. Moreover, since the contact area of the lead frame 32 with the resin portion of the base is large, the strength of the package against the shearing force is more enhanced. The measurement of the shearing force at the time when the package is broken was conducted in the same manner as the first embodiment. The shearing force was 4.8 kg. Thus, it was proved that the resin mold hollow package having the strength more closer to that of the ceramic package was obtained.
( Fourth Embodiment ) A package of a fourth embodiment of the present invention will be described with reference to Figs. 7(a) and 7(b}.
In the package of this embodiment, a nail portion 42b is formed in each portion of the lead frame 42 interposed between the base portion 43a and the bank portion 43b, in addition to the anchor hole 42a. The nail portion 42b is formed integrally with each of both sides of the lead frames 42. The nails portion 42b displays a tapering wedge shape with a top end extend-ing toward the outside of the base. The lead frame 42 having the nail portion 42b can be formed by press working or etching processing, similarly in the first embodiment. In this embodiment, the length and width of the nail portion 42b are set to be 0.2 mm, respec-tively. Other constitutions and materials of each portion of the package are the same as those of the first embodiment. The descriptions for them are omit-ted.
As described above, the formation of the nail portion 42b in the lead frame 42 enables to enhance the pulling-up strength of the lead frame 42. Particularly, the foregoing,wedge-shaped nail portion 42b enhances the pulling-up strength of the lead frame 42 more effectively.
Furthermore, it is possible to combine the anchor described in the second to fourth embodiments.

( Fifth Embodiment ) A package of a fifth embodiment of the present invention will be described with reference to Figs. 8(a) and 8(b).
The package of this embodiment of the present invention has a rectangular shape. A constitution thereof is principally similar to those of the forego-ing embodiments. Specifically, the resin portion of the base 51 includes a substrate portion 53(a) sealing the lead frame 52, and a frame-shaped bank portion 53b formed on the upper surface of the substrate portion 53 so as to nip the lead frame 52. Moreover, an anchor hole 52a is formed at the position of each lead frame 52 interposed between the substrate portion 53a and the bank portion 53b. Resin is filled also in the anchor hole 52a. The chip 54 is mounted on the position of the lead frame 52 surrounded by the bank portion 53b.
The chip 54 is electrically connected to the lead frame 52 by the bonding line 57. Then, the cap 55 is adhered to the upper surface of the base 51 by adhesive agent 56, whereby the chip 54 is sealed within the hollow space formed by the base 51 and the cap 55. The same materials as those of the foregoing embodiments are used to constitute each portion of the package.
The package of this embodiment is different from those of the foregoing embodiments in the following items. First, the bank portion 53b is arranged inside the inner wall of the cap 55. The cap 55 is adhered to the edge of the substrate portion 53a and the outer wall of the bank portion 53b. In this embodiment, the width of the bank portion 53b is set to be 0.35 mm and the height thereof is set to be 0.2 mm.
As described above, the bank portion 53b is arranged within the cap 55, and the cap 55 is adhered to the outer periphery of the substrate portion 53a and the outer wall of the bank portion 53b, whereby it is possible to increase the adhesion area and the adhesion strength. Moreover, it is possible to prevent the adhesive 56 from flowing into the hollow space.
Moreover, the cap 55 is adhered onto the substrate portion 53a, whereby the total height of the package can be reduced by an amount equal to the height of the bank portion 53b, compared to the foregoing embodiments. To be concrete, the total height of the package of this embodiment is 1.3 mm, though the total height of the package Qf the foregoing embodiments was 1.5 mm.
In addition to the above-described advantages, the bank portion 53b serves as a guide for the cap 55 at the time of adhering the cap 55 to the bank portion 53b, whereby a positioning accuracy of the cap 55 for the base 51 is enhanced. Furthermore, the strength of the cap 55 against for the shearing force is reinforced by the bank portion 53b.
( Sixth Embodiment ) A package of a sixth embodiment of the present invention will be described with reference to Figs. 9(a) and 9(b).
In the package of this embodiment, the lead frame 62 has a chip mounting portion 62b mounting the chip 64 and a bonding portion 62c connected electrically to the chip 64 through the bonding line 67, both portions 62b ar~i 62c being formed by bending the lead frame 62 in a convex shape. Thus, both portions 62b and 62c are exposed over the upper surface of the substrate portion 63a made of resin. The upper surface of the base 61 consisting of the substrate portion 63a and the lead frame 62 is flat. An anchor portion having an anchor hole 62a therein and serving.as a part of the lead frame 62 buried in the substrate portion 63a is located at a lower position than the chip mounting portion 62b and the bonding portion 62c. The lead frame 62 is projected from the side surface of the substrate portion 63a.
As described above, the lead frame 62 is bent at its portion within the substrate portion 63a, the anchor portion is disposed in the substrate portion 63a, and the lead frame 62 is projected from the side -- , -. ~~ 9s~~~
surface of the substrate portion 63a. With such shape of the lead frame 62, the pulling-up strength of the lead frame 62 is enhanced. In this embodiment, the -anchor hole 62a is not always necessary. It should be noted that concerning dimension of the major parts of the lead frame 62 of this embodiment, the heights H of the chip mounting portion 62b and the bonding portion 62c corresponding to the anchor portion are 0.2 mm, and the length L of the anchor portion is 0.4 mm, as shown in Fig. 10.
The cap 65 made of resin is adhered onto the upper surface of the substrate portion 63a by adhesive 66.
Thus, obtained is the resin mold package in which the chip 64 is sealed within the hollow portion formed of the base 61 and the cap 65. Therefore, the package of this embodiment has an excellent high frequency charac-teristic though it adopts resin as its material. The same materials for the lead frame 62, the substrate portion 63a, the cap 55, and the adhesive 66 as those of the foregoing embodiments are used.
A manufacturing method of the package 61 of this embodiment will be described. First, in the same manner as in the first embodiment, the lead frame 62 is formed in a specified shape. Subsequently, the lead frame 62 is subjected to emboss working by pressing whereby the chip mounting portion 62b and the bonding ~~ 96~6~
portion 62c are made convex shaped. Then, the lead frame 62 is disposed within a cavity surrounded by a metallic mold ( not shown ) and resin is injected into the cavity. Thus, the substrate portion 63a and the lead frame 62 are integrated with each other whereby the base 61 is formed.
Here, since the base 61 is obtained by molding integrally the lead frame 62 with resin using the metallic mold, resin flashes may occur on the surface of the chip mounting portion 62b and the bonding portion 62c depending on a clearance between the metallic mold and the lead frame 62. When theresin flashes occur at these portions, mounting of the chip - -64 will be difficult and connection of the chip 64 to the lead frame 62 will be impossible. The resin flashes must be removed before the chip 64 is mounted.
In this embodiment, the upper surface of the base 61 is formed in a flat shape, so that the removal of the flashes is easy, and the flashes are completely removed even when the flashes occur on the upper surface of the base 61.
In Japanese Patent Application Laid Open No.
Shouwa 64-11356, a semiconductor package analogous to that of this embodiment is disclosed. This semi-conductor package has, as shown in Fig. 16, a base 111.
The base 111 is an integrated body composed of a lead _ 28 _ frame 112 and a substrate portion 113a, the integration body being formed by molding the lead frame 112 with resin integrally. It is noted that the lead frame 112 is bent before molding of the lead frame I12 with resin. The uppermost portion of the lead frame 112 is exposed on the upper surface of the substrate portion 113a, and this exposed portion is connected to the chip 114 through the bonding line 117. The lowermost por-tion of the lead frame 112 is exposed on the bottom of the substrate portion 113a, and this exposed portion is soldered to a printed circuit board ( not shown ).
Since the lead frame 112 is exposed in upper and bottom portions of the substrate portion 113a and an outer lead can not be nipped by a metallic mold as in this embodiment, resin flashes occur at both surfaces of the substrate portion 113a when the base 111 is molded.
Therefore, in order to remove these resin flashes, working of removing the flashes must be conducted for the upper and bottom surfaces of the substrate portion 113a. However, in this embodiment, the working of removing the flashes only for the upper surface of the substrate portion 63a may do well. Therefore, in this embodiment, the number of the workings of removing the flashes is reduced compared to the package shown in Fig. 16.
Moreover, since the package shown in Fig. 16 has such constitution that the portion of the lead frame soldered to the printed circuit board is fixed to the substrate portion 113a, expansion and contraction of the printed circuit board due to thermal change direct- -ly act on the substrate portion 113a when the printed circuit board is mounted on a semiconductor package.
For this reason, a stress is applied to the substrate portion 113a so that cracks may occur in the substrate portion 113a. Contrary to the package shown in Fig.
I6, in the package of this embodiment, the lead frame 62 is projected from the side surface of the substrate -portion 63a. Moreover, the lead frame 62 is bent in its portion outside of the substrate portion 63a. The -expansion and contraction of the printed circuit board can be absorbed by the outside of the substrate portion 63a, whereby the stress is not almost applied to the substrate portion 63a.
( Seventh Embodiment ) A package of a seventh embodiment of the present invention will be described with reference to Figs. 11(a) and ll(b).
In Figs. 11(a) and 11(b), the base 71 consists of the lead frame 72, the substrate portion 73a sealing the lead frame 72, and 'the bank portion 73b formed on the substrate portion 73a, whereby the lead frame 72 is interposed between the substrate portion 73a and the .-2196268 _ bank portion 73b. The bank portion 73b is formed on all of the outer periphery of the substrate portion 73a, the bank portion 73b displaying a frame-like shape. Both of the substrate portion 73a and the bank portion 73b are made of resin, and they are integrally molded together with the lead frame 72 by a metallic mold ( not shown ). Thus, the lead frame 72 is inter-posed between the substrate portion 73a and the bank portion 73b whereby the lead frame 72 is held by them.
The anchor hole 72a is formed in each portion of the lead frame 72 which is interposed between the substrate portion 73a and the bank portion 73b. Resin is filled also in the anchor hole 72a at the time of resin sealing using the metallic mold. The diameter of the anchor hole 72a should be 0.1 mm or more in order to fill resin in the anchor hole 72a securely. For this reason, the width of the bank portion 73b may be 0.1 mm or more. As described above, the reason why the width of the bank portion 73b can be more reduced compared to the first embodiment is that the sealing resin 75 is filled in the region surrounded with the bank portion 73b, as described later, whereby the strength is ensured.
Furthermore, the bank portion 73b serves to hold the lead frame 72. Besides, the bank portion 73b is allowed to have a function to prevent the sealing resin 75 from flowing out therefrom. For this reason, the bank portion 73b should be high enough for the sealing resin 75 not to flow out from the bank portion 73b.
However, the height ~ralue varies according to an amount of the usage of the sealing resin 75 and it is not limited to that value.
The chip 74 is mounted on the region surrounded by the bank portion 73b. Moreover, the chip 74 is sealed with the sealing resin 75 which is dropped from the above in a liquid state. The sealing resin 75 fills ~e ~gion surrounded by the bank portion 73b. The sealing resin 75 is solidified after being dropped. A
plurality of projection electrodes 77 are formed on an electrode formation surface of the chip 74. Then, the electrode formation surface is placed upside down, and the lead frame 72 and the projection electrode 77 are connected.
The projection electrode 77 is set to be high enough such that the sealing resin 75 does not flow inside the projection electrode 77 when the sealing resin 75 is dropped down. Furthermore, a space is formed between the chip 74 and the substrate portion 73a. For example, when epoxy resin having viscosity of about 1040 cp is used as the sealing resin 75, the height of the projection electrode 77 must be 0.07 mm or less.

.- 219 6268 Next, an example of a manufacturing method of the package of this embodiment will be described with reference to Figs. 12(a) to 12(c). First, the lead frame formed in a specified shape by a press working or an etching processing is disposed within a cavity of a metallic mold ( not shown ). Resin is injected into this cavity, whereby the base 71 composed of the substrate portion 73a, the bank portion 73b, and the lead frame 72 integrated with each other is formed ( Fig. 12(a) ).
Subsequently, a gold ball is formed on each of the projection electrodes 77 of the chip 74 by bonding. A
gold wire for the formation of the gold ball may be one having a diameter of 20 um which has been well used.
Thereafter, the lead frame 72 is heated to temperature between 260°C and 280°C. At this situation, the pro-jection electrode 77 is directed downward, and the chip 74 is disposed above the lead frame 72. Subsequently, the projection electrode 77 and the lead frame 72 are thermally bonded by compressing ( Fig. 12(b) ).
Upon completion of the connection of the projection electrode 77 to the lead frame 72, the sealing resin 75 is dropped into the region surrounded by the bank portion 73b, whereby the chip 74 is sealed ( Fig. 12(c) ). Thus, a space is formed between the electrode formation surface of the chip 74 and the lead 2196268 _ frame 72. The quantity o~ the sealing resin 75 to be Chopped shall be the one to seal the chip 74 perfectly when the sealing resin 75 is filled in the region surrounded by the bank portion 73b. Furthermore, these steps should be preferably conducted at a reduced -pressure condition, in order to prevent occurrence of -cracks in the chip 74.
As described above, the projection electrode 77 formed in the chip 74 is faced the lead frame 72, and the chip 74 and the lead frame 72 are connected. Then, the chip 74 is sealed by the dropped sealing resin 75.
Thus, the resin mold package having an excellent high frequency characteristic can be obtained, which has the space in the electrode formation surface of the chip 74. Furthermore, although the space facing the elec-trode formation surface of the chip 74 is formed, the outer surface of the chip 74 is sealed by the sealing resin 75. Therefore, a mechanical strength of the package of this embodiment is excellent. Particularly, by connecting between the substrate portion 73a and the bank portion 73b through the anchor hole 72a, a pull- -ing-up strength of the lead frame 72 is also enhanced.
Furthermore, the manufacturing techniques of the con-ventional resin sealing package can be utilized, with out any modification, concerning molding of the base 71 and mounting of the chip 74. Therefore, the high level techniques is not required so much for dropping the sealing resin 75. Therefore, the package of this embodiment of the present invention can be manufactured easily and inexpensively by almost the same manufactur-ing steps as those of the conventional resin sealing package.
( Eighth Embodiment ) A package of an eighth embodiment of the present invention will be described with reference to Figs. I3(a) and 13{b).
In the package of this embodiment, a frame-shaped inner side bank portion 83c is arranged on the upper -surface of the base 81 and inside the bank portion 83b, in addition to the bank portion 83b. The inner side bank portion 83c is located outside the projection electrode-87, mounting the chip 84 thereon. The electrode formation surface of the chip 84 attaches tightly to the inner side bank portion 83c all over the outer periphery thereof. The inner side bank portion 83c is formed simultaneously when the substrate portion 83a and the bank portion 83b are formed at the time of molding the base 81.-- In order to attach the upper surface of the inner side bank portion 83c with the electrode formation surface of the chip 84 securely, the height of the inner side bank portion 83c should be preferably larger than the distance between the chip 84 and the lead frame 82. The connection of the projection electrode 87 to the lead frame 82 should not be hindered. Therefore, in this embodiment, the height of the inner side bank portion 83c is set to be larger than the distance between the chip 84 and the lead frame 82 by 5 to 10 Vim. Other constitutions of the package of this embodiment is the same as those of the seventh embodiment, and the descriptipns for them are omitted.
Next, a manufacturing method of the package of this embodiment will be described with reference to Figs. 14(a) to 14(c).
First, the lead frame 82 which was previously formed in a specified shape by press working or etching processing is disposed within a cavity of a metallic mold ( not shown ). Resin is injected into the cavity, thereby forming the base 81 consisting of the substrate portion 83a, the bank portion 83b, the inner side bank portion 83c, and the lead frame 82, which are integrat-ed with each other ( Fig. 14(a) ).
Subsequently, in the same manner as the seventh embodiment, the projection electrode 87 and the lead frame 82 are thermally compressed to be fixed to each other. Thus, the upper surface of the inner side bank portion 83c and outer periphery of the electrode forma-tion surface of the chip 84 are adhered closely, where-CA 02196268 2000-OS-04' by the space formed by the inner side bank portion 83c and the chip 84 is sealed hermetically ( Fig. 14(b) ).
Upon completion of the connection of the projection electrode 87 to the lead frame 82, the sealing resin 8~ is dropped in the same manner as the seventh embodiment, whereby the chip 84 is sealed ( Fig. 14(c) ). At this time, since the inside of the inner side bank portion 83c is sealed hermetically as described above, the sealing resin 85 is prevented from flowing into the inside of the inner side bank portion 83c, whereby the space for the electrode formation surface of the chip 84 can be secured.
In this embodiment, it is possible to prevent the sealing resin 85 from flowing into the electrode forma-tion surface of the chip 84 by means of the inner side bank portion 83c. Therefore, there is no restriction to the viscosity of the sealing resin 85 and the height of the projection electrode 87, which is needed in the seventh embodiment.
As described above, according to the present invention, the principal structure of the package is that the package is made of resin, the chip is sealed in the space formed by the base and the cap, or the chip is sealed in the space formed between the lead frame and the electrode formation surface facing the lead frame. Therefore, the resin mold hollow package 2~ 9658 having an excellent high frequency characteristic can be obtained.
Among those packages, in the package in which the bank portion is formed on the upper surface and at the periphery of the substrate portion of the base, the anchor portion is formed at the portion of the lead frame interposed between the substrate portion and the bank portion, and the cap is fixed to the bank portion, the strength of the package itself can be increased.
Particularly, the pulling-up strength of the lead frame can be also increased by forming the blade portion, the jagged stripe or the nail portion in the lead frame, or by adding the anchor portion obtained by combining them to the lead frame.
Furthermore, in the package in which the bank portion is arranged inside the inner wall of the cap, -and the cap is fixed to the outer surface of the bank portion and the edge of the substrate portion, not only the strength of the package itself but also the fixing strength of the cap can be increased by the bank por-tion. In addition, the bank portion serves as a guide for the cap, whereby the accuracy in positioning at the time of fixing the cap to the base can be increased.
Furthermore, in the package in which the lead frame is bent in a convex shape so as to expose its chip mounting portion and bonding portion to the sur-face of the substrate portion, and the lead frame is projected from the side surface of the substrate por-tion, the pulling-up strength of the lead frame can be increased without formation of the bank portion. In this case, by making the upper surface of the lead frame flat, flashes of the resin occurred in the sur-face of the lead frame at the time of formation of the base will be easily removed.
Furthermore, in the package in which the chip having a plurality of projection electrodes with the electrode formation surface facing the lead frame of the base is connected to the lead frame, and the chip is sealed with the sealing resin dropped from the above, it is possible to increase the strength of the package itself by the sealing resin. Particularly, the formation of the inner side bank portion in the base prevents the sealing resin from flowing into the space between the chip and the lead frame and makes the secure formation of this space possible.
Although the preferred embodiment of the present invention has been described in detail, it should be understood that various changes, substitutions and alternations can be made therein without departing from spirit and scope of the inventions as defined by the appended claims.

Claims (17)

1. A package comprising:
a base including a lead frame, a substrate portion sealing said lead frame therein, a framed-shaped bank portion formed at an outer periphery of an upper surface of said substrate portion, said bank portion having said lead frame interposed between said bank portion and the substrate portion, and an anchor portion formed in a portion of said lead frame interposed between said substrate portion and said bank portion, said substrate portion and said bank portion being formed integrally with said lead frame by resin;
a chip electrically connected to said lead frame and mounted on a region of said lead frame on said base, said region being surrounded by said bank portion; and a cap made of resin covering said chip, said cap being fixed onto said bank portion and having a recess therein which cooperates with the base to form a cavity for housing the chip.
2. The package according to claim 1, wherein said anchor portion is an anchor hole formed at a portion of said lead frame interposed between said substrate portion and said bank portion, said anchor hole connects said substrate portion to said bank portion.
3. The package according to claim 1, wherein said anchor portion consists of an anchor hole and a blade portion, said anchor portion being formed at a portion of said lead frame interposed between said substrate portion and said bank portion and connecting, said substrate portion to said bank portion, and said blade portion projects toward a direction of a thick-ness of said lead frame.
4. The package according to claim 3, wherein said blade portion projects toward a side surface of said bank portion.
5. The package according to claim 1, wherein said anchor portion, which is formed at a portion of said lead frame interposed between said substrate portion and said bank portion, consists of an anchor hole and jagged stripes, said anchor hole connecting said substrate portion to said bank portion and said jagged stripes having tops and bottoms alternately arranged along a direction of a width of said lead frame.
6. The package according to claim 1, wherein said anchor portion consists of an anchor hole and a nail portion formed at a portion of said lead frame interposed between said substrate portion and said bank portion, said anchor hole connecting said substrate portion to said bank portion.
7. The package according to claim 6, wherein said nail portion displays a tapering wedge shape with a top end extending toward an outside of said base.
8. A package comprising:
a base including a lead frame, a substrate portion sealing said lead frame therein, and a frame-shaped bank portion formed on an upper surface of said substrate portion, said bank portion having said lead frame interposed between said bank portion and the substrate portion, and said substrate portion and said bank portion being formed integrally with said lead frame by resin;
a chip electrically connected to said lead frame and mounted on a region of said lead frame on said base, said region being surrounded by said bank portion; and a cap made of resin covering the said chip, said cap being fixed onto said bank portion and having a recess therein which cooperates with the base to form a cavity for housing the chip:
wherein said bank portion is arranged inside an inner wall of said cap, and said cap is fixed to an edge of said substrate portion and an outer wall surface of said bank portion.
9. The package according to claim 8, wherein an anchor portion is provided at a portion of said lead frame interposed between said substrate portion and said bank portion.
10. The package according to claim 9, wherein said anchor portion is an anchor hole formed in said lead frame, said
11. A package comprising:
a base including a lead frame and a substrate portion in which said lead frame is sealed therein, said substrate portion being formed integrally with said lead frame;
a chip mounted on a portion of said lead frame disposed on said base, said chip being electrically connected to said lead frame; and a cap made of resin fixed to said base, said cap covering said chip and having a recess therein which cooperates with the base to form a cavity for housing the chip, wherein said lead frame has a chip mounting portion for mounting said chip and a bonding portion electrically connected to said chip, said chip mounting portion and said bonding portion being bent in a convex shape so as to-be exposed to a surface of said sub-strate portion, and said lead frame being projected from a side surface of said substrate portion.
12. The package according to claim 11, wherein an upper surface of said base is made flat.
13. A package comprising:
a base including a lead frame, a substrate portion sealing said lead frame-therein, and a frame-shaped bank portion formed at an outer periphery of an upper surface of said substrate portion, said bank portion having said lead frame interposed between said bank portion and said substrate portion, and said substrate portion and said bank portion being formed integrally with said lead frame by resin; and a chip mounted on a region surrounded by said bank portion in said lead frame on said base, said chip being electrically connected to said lead frame:
wherein said chip, which has a plurality of projection electrodes on its electrode formation surface facing said lead frame, is connected to said lead frame and is sealed with dropped resin, and a space is provided between said chip and said substrate portion.
14. The package according to claim 13, wherein a frame-shaped inner side bank portion is formed on an upper surface of said base, said inner bank portion being located at a position between said bank portion and said projection electrodes and being fixed to all portion of an outer periphery of the electrode formation surface of said chip.
15. The package according to claim 14, wherein said inner side bank portion is made of resin and said inner side bank portion is molded simultaneously together with said substrate portion and said bank portion.
16. The package according to claim 14, wherein said lead frame has an anchor portion formed at a position interposed between said substrate portion and said bank portion.
17. The package according to claim 16, wherein said anchor portion is an anchor hole formed in said lead frame, said anchor hole connecting said substrate portion to said bank portion.
CA002196268A 1996-02-01 1997-01-29 Package Expired - Fee Related CA2196268C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP016680/1996 1996-02-01
JP8016680A JP2842355B2 (en) 1996-02-01 1996-02-01 package

Publications (2)

Publication Number Publication Date
CA2196268A1 CA2196268A1 (en) 1997-08-02
CA2196268C true CA2196268C (en) 2001-10-02

Family

ID=11923037

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002196268A Expired - Fee Related CA2196268C (en) 1996-02-01 1997-01-29 Package

Country Status (7)

Country Link
US (1) US5905301A (en)
EP (1) EP0788157A3 (en)
JP (1) JP2842355B2 (en)
KR (1) KR100231118B1 (en)
AU (1) AU736114B2 (en)
CA (1) CA2196268C (en)
TW (1) TW390002B (en)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19629767C2 (en) * 1996-07-23 2003-11-27 Infineon Technologies Ag Connection frames for semiconductor chips and semiconductor modules
WO1999023700A1 (en) 1997-11-05 1999-05-14 Martin Robert A Chip housing, methods of making same and methods for mounting chips therein
US6329705B1 (en) 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
JP3536722B2 (en) * 1998-06-18 2004-06-14 松下電器産業株式会社 Chip type solid electrolytic capacitor and method of manufacturing the same
JP3051376B2 (en) * 1998-08-24 2000-06-12 松下電子工業株式会社 Lead frame, method for manufacturing the same, and semiconductor device using lead frame
SG92624A1 (en) * 1999-02-09 2002-11-19 Inst Of Microelectronics Lead frame for an integrated circuit chip (integrated circuit peripheral support)
JP3724979B2 (en) * 1999-04-27 2005-12-07 富士通株式会社 Semiconductor device
US6274927B1 (en) * 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
JP2000349178A (en) * 1999-06-08 2000-12-15 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
DE10004410A1 (en) * 2000-02-02 2001-08-16 Infineon Technologies Ag Semiconductor device for discrete device with contacts on lower side - has second metallisation provided on second main side of chip, lying flush with surface, for carrying signals
JP2002009581A (en) * 2000-06-26 2002-01-11 Toshiba Corp Surface acoustic wave device
JP2002057253A (en) * 2000-08-10 2002-02-22 Nec Corp Semiconductor device and method of manufacturing the same
US6433424B1 (en) * 2000-12-14 2002-08-13 International Rectifier Corporation Semiconductor device package and lead frame with die overhanging lead frame pad
US6861720B1 (en) 2001-08-29 2005-03-01 Amkor Technology, Inc. Placement template and method for placing optical dies
US6784534B1 (en) 2002-02-06 2004-08-31 Amkor Technology, Inc. Thin integrated circuit package having an optically transparent window
EP1403926A2 (en) 2002-09-27 2004-03-31 Matsushita Electric Industrial Co., Ltd. Semiconductor device
SG157957A1 (en) * 2003-01-29 2010-01-29 Interplex Qlp Inc Package for integrated circuit die
DE502004000545D1 (en) * 2003-02-13 2006-06-14 Infineon Technologies Ag ELECTRONIC COMPONENT WITH SEMICONDUCTOR CHIP AND METHOD FOR THE PRODUCTION THEREOF
JP3898666B2 (en) * 2003-04-28 2007-03-28 松下電器産業株式会社 Solid-state imaging device and manufacturing method thereof
JP4106003B2 (en) * 2003-09-03 2008-06-25 松下電器産業株式会社 Method for manufacturing solid-state imaging device
JP4147171B2 (en) * 2003-10-23 2008-09-10 松下電器産業株式会社 Solid-state imaging device and manufacturing method thereof
JP4698234B2 (en) * 2005-01-21 2011-06-08 スタンレー電気株式会社 Surface mount semiconductor device
KR100638721B1 (en) * 2005-01-28 2006-10-30 삼성전기주식회사 Side view led package having lead frame structure designed for improving resin flow
JP2007201376A (en) * 2006-01-30 2007-08-09 Yamaha Corp Semiconductor device
US8344487B2 (en) 2006-06-29 2013-01-01 Analog Devices, Inc. Stress mitigation in packaged microchips
JP5133598B2 (en) * 2007-05-17 2013-01-30 日東電工株式会社 Thermosetting adhesive sheet for sealing
JP2009283553A (en) * 2008-05-20 2009-12-03 Nec Electronics Corp Electronic device and method of manufacturing the same
JP2010232243A (en) * 2009-03-26 2010-10-14 Renesas Electronics Corp Method for manufacturing semiconductor device
JP2011200398A (en) * 2010-03-25 2011-10-13 Fujifilm Corp Endoscope
US9676614B2 (en) 2013-02-01 2017-06-13 Analog Devices, Inc. MEMS device with stress relief structures
EP2797111A1 (en) * 2013-04-24 2014-10-29 Nxp B.V. Electrical component packaging
JP6201626B2 (en) * 2013-10-23 2017-09-27 スミダコーポレーション株式会社 Electronic component and method for manufacturing electronic component
US10167189B2 (en) 2014-09-30 2019-01-01 Analog Devices, Inc. Stress isolation platform for MEMS devices
JP6256301B2 (en) * 2014-10-31 2018-01-10 株式会社デンソー Electronic circuit components
JP7049611B2 (en) * 2015-09-01 2022-04-07 マコム テクノロジー ソリューションズ ホールディングス， インコーポレイテッド Air cavity package
US10131538B2 (en) 2015-09-14 2018-11-20 Analog Devices, Inc. Mechanically isolated MEMS device
JP6477421B2 (en) * 2015-10-29 2019-03-06 三菱電機株式会社 Semiconductor device
JP6658104B2 (en) * 2016-03-01 2020-03-04 株式会社デンソー Circuit device
CN108847442B (en) * 2018-06-30 2022-01-25 山东昊润自动化技术有限公司 Pressure chip packaging method
CN108989511B (en) * 2018-09-25 2023-05-12 苏州昀冢电子科技股份有限公司 Base with electronic element and voice coil motor
JP7005469B2 (en) * 2018-11-07 2022-02-04 三菱電機株式会社 Semiconductor device
US11417611B2 (en) 2020-02-25 2022-08-16 Analog Devices International Unlimited Company Devices and methods for reducing stress on circuit components
US11981560B2 (en) 2020-06-09 2024-05-14 Analog Devices, Inc. Stress-isolated MEMS device comprising substrate having cavity and method of manufacture
CN116435201B (en) * 2023-06-12 2023-09-12 四川遂宁市利普芯微电子有限公司 Plastic packaging method and device packaging structure

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1144380A (en) * 1966-01-03 1969-03-05 Texas Instruments Inc Process for fabricating hermetic seals
JPS5422770A (en) * 1977-07-22 1979-02-20 Hitachi Ltd Lead frame
JPS5662344A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Resin sealed semiconductor device
JPS5710954A (en) * 1980-06-25 1982-01-20 Nec Corp Semiconductor device
JPS58134449A (en) * 1982-02-04 1983-08-10 Sharp Corp Lsi package
JPS5943526A (en) * 1982-09-03 1984-03-10 Matsushita Electric Works Ltd Manufacture of resin sealed type electronic part
JPS59169161A (en) * 1983-03-16 1984-09-25 Hitachi Ltd Semiconductor device
JPS61128551A (en) * 1984-11-27 1986-06-16 Toshiba Corp Lead frame for semiconductor device
IL80270A0 (en) * 1985-10-11 1987-01-30 Cird Naphthalene derivatives,their preparation and pharmaceutical compositions containing them
JPS6298751A (en) * 1985-10-25 1987-05-08 Toshiba Corp Semiconductor enclosure for resin sealing
JPS63222452A (en) * 1987-03-11 1988-09-16 Mitsubishi Electric Corp Resin seal type semiconductor device
JP2523637B2 (en) * 1987-05-27 1996-08-14 株式会社日立製作所 Semiconductor device
JP2600689B2 (en) * 1987-07-06 1997-04-16 ソニー株式会社 Hollow package for semiconductor device
JPS6480058A (en) * 1987-09-21 1989-03-24 Nec Corp Semiconductor device
JPH0225057A (en) * 1988-07-13 1990-01-26 Mitsubishi Electric Corp Manufacture of semiconductor device
JP2598129B2 (en) * 1989-05-18 1997-04-09 三菱電機株式会社 Semiconductor device
JPH0330362A (en) * 1989-06-27 1991-02-08 Mitsubishi Electric Corp Lead frame for integrated circuit and manufacture thereof
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
JPH04150057A (en) * 1990-10-12 1992-05-22 Nec Corp Package for semiconductor device
JPH04246847A (en) * 1991-02-01 1992-09-02 Nec Kyushu Ltd Package of semiconductor integrated circuit
JPH04303946A (en) * 1991-03-29 1992-10-27 Mitsubishi Electric Corp Semiconductor device
JP3207222B2 (en) * 1991-08-29 2001-09-10 株式会社東芝 Electronic component equipment
JPH05226548A (en) * 1991-11-27 1993-09-03 Samsung Electron Co Ltd Lead frame for semiconductor device use
JPH05291319A (en) * 1992-04-07 1993-11-05 Toshiba Corp Resin sealing-type semiconductor device
TW332348B (en) * 1992-06-23 1998-05-21 Sony Co Ltd Manufacturing method for solid state motion picture device provides a highly accurate and low cost solid state motion picture device by use of empty package made of resin.
JPH0661383A (en) * 1992-08-11 1994-03-04 Fujitsu Ltd Semiconductor device
JPH0661365A (en) * 1992-08-11 1994-03-04 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0669366A (en) * 1992-08-21 1994-03-11 Ricoh Co Ltd Semiconductor device mounting body and mounting method
JP2828553B2 (en) * 1992-12-17 1998-11-25 京セラ株式会社 Semiconductor device
US5557144A (en) * 1993-01-29 1996-09-17 Anadigics, Inc. Plastic packages for microwave frequency applications
US5497032A (en) * 1993-03-17 1996-03-05 Fujitsu Limited Semiconductor device and lead frame therefore
US5548087A (en) * 1993-05-07 1996-08-20 At&T Corp. Molded plastic packaging of electronic devices
JP2875139B2 (en) * 1993-07-15 1999-03-24 株式会社東芝 Method for manufacturing semiconductor device
US5362679A (en) * 1993-07-26 1994-11-08 Vlsi Packaging Corporation Plastic package with solder grid array
JP2937713B2 (en) * 1993-10-25 1999-08-23 株式会社東芝 Semiconductor device
JPH0855927A (en) * 1994-08-12 1996-02-27 Mitsui Petrochem Ind Ltd Hollow package
JPH0875580A (en) * 1994-09-06 1996-03-22 Mitsubishi Electric Corp Semiconductor pressure sensor
US5610442A (en) * 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus

Also Published As

Publication number Publication date
CA2196268A1 (en) 1997-08-02
EP0788157A2 (en) 1997-08-06
AU736114B2 (en) 2001-07-26
US5905301A (en) 1999-05-18
TW390002B (en) 2000-05-11
JPH09213826A (en) 1997-08-15
JP2842355B2 (en) 1999-01-06
KR100231118B1 (en) 1999-11-15
AU1238697A (en) 1997-08-07
EP0788157A3 (en) 2004-02-25
KR970063696A (en) 1997-09-12

Similar Documents

Publication Publication Date Title
CA2196268C (en) Package
US6410979B2 (en) Ball-grid-array semiconductor device with protruding terminals
US6983537B2 (en) Method of making a plastic package with an air cavity
US9087924B2 (en) Semiconductor device with resin mold
KR100341104B1 (en) semiconductor device assembly method and semiconductor device produced by the method
JPH06302604A (en) Resin-sealed semiconductor package and fabrication thereof
EP0644587B1 (en) Semiconductor package and fabrication method
JP3406270B2 (en) Semiconductor device and manufacturing method thereof
KR19990076568A (en) Resin molding semiconductor device and manufacturing method of semiconductor package
US8138025B2 (en) Microcap wafer bonding method and apparatus
EP0807973B1 (en) Plastic molded type semiconductor device and method of manufacturing the same
US6002181A (en) Structure of resin molded type semiconductor device with embedded thermal dissipator
EP0210371A1 (en) Semiconductor device having a plurality of leads
JP2008034601A (en) Semiconductor device and manufacturing method thereof
US6404100B1 (en) Surface acoustic wave apparatus and method of manufacturing the same
US6429517B1 (en) Semiconductor device and fabrication method thereof
JPH06342816A (en) Semiconductor device, its manufacture, and lead frame used therefor
JPH07211847A (en) Semiconductor device, its manufacture, its mounting structure and mounting method
CN111584435B (en) Substrate, chip packaging structure and preparation method thereof
TW454317B (en) Manufacturing method of semiconductor package device with flash-prevention structure
KR20080101207A (en) Mold resin effluence prevention case
KR100308899B1 (en) semiconductor package and method for fabricating the same
CN108831839B (en) Method for removing burrs generated in semiconductor plastic packaging process
KR100643333B1 (en) Light emitting diode package having a reflector cup by metal thin film and its manufacturing method
JP3181935B2 (en) IC card

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20160129