JPS6298751A - Semiconductor enclosure for resin sealing - Google Patents
Semiconductor enclosure for resin sealingInfo
- Publication number
- JPS6298751A JPS6298751A JP60237513A JP23751385A JPS6298751A JP S6298751 A JPS6298751 A JP S6298751A JP 60237513 A JP60237513 A JP 60237513A JP 23751385 A JP23751385 A JP 23751385A JP S6298751 A JPS6298751 A JP S6298751A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- resin
- semiconductor element
- sealing resin
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体素子特に集積回路素子に好適する樹脂製
外囲器の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in resin envelopes suitable for semiconductor devices, particularly integrated circuit devices.
従来の半導体素子用の外囲器としては封止用樹脂として
エポキシ樹脂もしくはシリコン樹脂等の熱硬化性樹脂を
使用してトランスファモールド法によって成形するのが
普通であるが、これを第２〜第３図により詳しく説明す
る。Conventional envelopes for semiconductor devices are usually molded by transfer molding using a thermosetting resin such as epoxy resin or silicone resin as the sealing resin. This will be explained in detail in Figure 3.
第２図には従来から多用されているＤＩＰ型樹脂外囲器
の断面図を示し、半導体素子（２０）がリードフレーム
（２１）のベッド部にダイボンディングされ、この半導
体素子の電極とリードフレーム（２１）間に差し渡した
金属細線（２２）を熱圧着法によって固定してから熱硬
化性樹脂によって封止樹脂層（２３）を全体に被覆する
。従って、この封止樹脂層（２３）は半導体素子（２０
）及び金属細線（２２）と直接接触しているために、５
〜１６時間にわたって２次キュア処理を施して封止樹脂
中の極性基を完全に架橋して、半導体素子の稼動による
昇温時での安定性を維持している。FIG. 2 shows a cross-sectional view of a conventionally widely used DIP type resin envelope, in which a semiconductor element (20) is die-bonded to the bed part of a lead frame (21), and the electrodes of this semiconductor element and the lead frame (21) After fixing the thin metal wire (22) interposed therebetween by thermocompression bonding, the whole is covered with a sealing resin layer (23) with a thermosetting resin. Therefore, this sealing resin layer (23) covers the semiconductor element (20).
) and the thin metal wire (22),
Secondary curing treatment is performed for ~16 hours to completely crosslink the polar groups in the sealing resin, thereby maintaining stability even when the temperature rises due to operation of the semiconductor element.
第３図にはこのトランスファモールド法における金型断
面図を示した。上型（２４）と下型（２５）の間に、半
導体素子をマウントしたリードフレームを挟み型締めし
てから予熱した封止用樹脂（２３）をポット（２６）に
装入し１次いで上型（２４）と下型（２５）により加熱
した封止用樹脂（２３）をプランジャ（２７）で押圧し
て溶融した樹脂（２３）をランナ（２８）とゲート（２
９）を通過させてキャビティ（３０）内に流入する。FIG. 3 shows a cross-sectional view of a mold in this transfer molding method. A lead frame with a semiconductor element mounted thereon is sandwiched between the upper mold (24) and the lower mold (25), the molds are clamped, and preheated sealing resin (23) is charged into the pot (26). The sealing resin (23) heated by the mold (24) and lower mold (25) is pressed by the plunger (27), and the melted resin (23) is transferred to the runner (28) and the gate (2).
9) and flows into the cavity (30).
一定の硬化時間（約２〜３分）経過後、金型をはずして
キャビティ（３０）の形状に沿って形成品を取出す。After a certain curing time (about 2 to 3 minutes) has elapsed, the mold is removed and the molded product is taken out along the shape of the cavity (30).
また、あらかじめ熱可塑性樹脂を用いた成型品を超音波
溶接法でインサート微小部品と溶融接合するキャビティ
パッケージを形成する方法も試みられたが超音波による
振動によりインサート部の破断を起し、更に構造上耐湿
保護に難点を生じる。In addition, attempts have been made to form a cavity package by melt-bonding a molded product made of thermoplastic resin with a microinsert component using ultrasonic welding, but the vibration caused by the ultrasonic wave causes the insert to break, resulting in further damage to the structure. This causes difficulties in moisture protection.
従来のトランスファモールド法による樹脂封止工程によ
る半導体装置では樹脂の熱的変形による応力によりペレ
ットクラック、特性変動、熱圧着法によって固定した金
属細線への悪影響を与え易い。In a semiconductor device using a resin sealing process using the conventional transfer molding method, stress caused by thermal deformation of the resin tends to cause pellet cracks, characteristic fluctuations, and adverse effects on the thin metal wire fixed by the thermocompression bonding method.
しかし、この悪影響の軽減化や半導体装置の電気的＋、
ｌｆ性から使用する成形樹脂の種類が規制される。この
ため外囲器の持つ重要な機能である耐湿性だけからみれ
ば必ずしも満足できない場合が多いし、又熱可塑性樹脂
の使用は耐湿性が不充分となる。However, it is possible to reduce this negative effect and improve the electrical performance of semiconductor devices.
The type of molding resin used is regulated based on its lf properties. For this reason, moisture resistance, which is an important function of the envelope, is often not always satisfactory, and the use of thermoplastic resin results in insufficient moisture resistance.
本発明は上記難点を除去した新規な樹脂封止用半導体外
囲器を提供するもので、セラミックならびに金属封止並
みの高信頼性を得るものである。The present invention provides a novel resin-sealed semiconductor envelope that eliminates the above-mentioned drawbacks and achieves high reliability comparable to ceramic and metal seals.
上記目的を達成するために本発明に係る外囲器ではリー
ドフレームにマウントする半導体素子ならびにこれとリ
ードフレーム間を接続する金属細線付近に空所を設けて
封止樹脂との密着による難点を除去する手法を採用して
信頼性を向上する。In order to achieve the above object, in the envelope according to the present invention, a space is provided near the semiconductor element mounted on the lead frame and the thin metal wire connecting the semiconductor element and the lead frame to eliminate the difficulty caused by close contact with the sealing resin. Improve reliability by adopting methods to improve reliability.
第１図（ａ）〜（ｄ）により本発明を詳述する。 The present invention will be explained in detail with reference to FIGS. 1(a) to (d).
本発明に係る外囲器■の最終構造は第１図（ｃ）ならび
に（ｄ）の断面図に示したが、この製造はトランスファ
モールド法を利用するので第２図及び第３図を利用して
説明する。リードフレームとしてはＤＩＰ型を示した。The final structure of the envelope (2) according to the present invention is shown in the cross-sectional views of FIGS. I will explain. A DIP type lead frame is shown.
第３図にはトランスファモールド工程に利用する金型構
造が示されているが、この上型（２４）と下型（２５）
の間にＤＩＰ型のリードフレームを挟み、型締めを行っ
てから予熱した封止用熱硬化性樹脂（２３）をポット（
２６）に装入し、次いで上型（２４）と下型（２５）に
より加熱された封止用樹脂（２３）をプランジャ（２７
）で押圧して、溶融した樹脂（２３）をランナ（２８）
とゲート（２９）を通過させてキャビティ（３０）内に
流入する。Figure 3 shows the mold structure used in the transfer molding process, where the upper mold (24) and lower mold (25)
After sandwiching a DIP type lead frame between them and clamping the mold, preheated thermosetting resin for sealing (23) is placed in a pot (
26), and then the sealing resin (23) heated by the upper mold (24) and lower mold (25) is transferred to the plunger (27).
) to transfer the melted resin (23) to the runner (28).
The water passes through the gate (29) and flows into the cavity (30).
このキャビティ（３０）には特殊な冶具を設置して第１
図（、）に示す断面形状の樹脂成形品を得る。A special jig is installed in this cavity (30) and the first
A resin molded product having the cross-sectional shape shown in the figure (,) is obtained.
この場合熱硬化性樹脂を利用するので、２〜３分程度の
硬化時間経過後、金型をはずしてキャビティ（３０）の
形状に合った成形品を得る。この結果リードフレームよ
り下方全面にわたって封止樹脂（２３）があり、それに
対向する封止樹脂（２３）は、その中央部分に空間があ
る環状樹脂（υが形成され、この空間部分■にリードフ
レーム（２１）のベット部■が露出する。次にこのベッ
ト部■に第２図に示すように半導体素子（２０）をマウ
ント固定後金属細線（２２）によって半導体素子に形成
した電極とリードフレーム間を熱圧着法によって接続す
る。次に環状樹脂間にセラミックス、ガラスもしくは樹
脂よりなる蓋体（イ）によって封止する。In this case, since a thermosetting resin is used, the mold is removed after curing time of about 2 to 3 minutes to obtain a molded product that matches the shape of the cavity (30). As a result, there is a sealing resin (23) over the entire surface below the lead frame, and the sealing resin (23) opposite to it is formed into an annular resin (υ) with a space in the center, and this space part ■ is filled with the lead frame. The bed part (21) is exposed.Next, as shown in Figure 2, the semiconductor element (20) is mounted and fixed on this bed part (■), and then the electrodes formed on the semiconductor element and the lead frame are connected using thin metal wires (22). are connected by thermocompression bonding.Next, the annular resin is sealed with a lid (a) made of ceramic, glass, or resin.
一方、金属細線（２２）のループ高さを一定に維持する
ために、前述のトランスフモールド法程におけるキャビ
ティ内に設置する治具形状を変えて突起物■を設置して
も良い。On the other hand, in order to maintain the loop height of the thin metal wire (22) constant, the protrusion (2) may be installed by changing the shape of the jig installed in the cavity in the above-described transfer molding process.
このように本発明に係る外囲器は金属細線及び半導体素
子は封止樹脂と密着せずに構成する。In this manner, the envelope according to the present invention is configured such that the thin metal wires and the semiconductor element are not in close contact with the sealing resin.
〔発明の効果〕
本発明に係る外囲器は半導体素子を設置する以前に予め
前述のように空間を設けた構造に樹脂形成しているので
金属細線に直接密着しておらず、その熱的変形に伴う応
力による悪影響を皆無にするばかりでなく、外囲器の成
形時には耐湿性を考慮して適用樹脂の選択自由度を増す
ことができる。[Effects of the Invention] The envelope according to the present invention is formed of resin in a structure in which a space is provided in advance as described above before installing the semiconductor element, so it is not in direct contact with the thin metal wire, and its thermal Not only can the adverse effects of stress associated with deformation be completely eliminated, but also moisture resistance can be taken into consideration when molding the envelope, increasing the degree of freedom in selecting the resin to be applied.
第１図（ａ）〜（ｄ）は本発明の実施例の工程順を示す
断面図、第２図は従来の樹脂封止型半導体装置断面図、
第３図はそのトランスファモールド金型の断面図である
。FIGS. 1(a) to (d) are cross-sectional views showing the process order of an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional resin-sealed semiconductor device,
FIG. 3 is a sectional view of the transfer mold die.
Claims (1)
ドフレームのリード間を金属細線で接続したマウント構
体を樹脂でトランスファモールドし、このリードを封止
樹脂外に導出する外囲器において、リードフレームを境
に積層する封止樹脂層にこの半導体素子近傍に空間部を
設けて得られる環状封止樹脂層に差し渡す絶縁物層を封
止することを特徴とする樹脂封止用半導体外囲器。The mount structure, in which the electrodes of the semiconductor element fixed to the lead frame and the leads of this lead frame are connected by thin metal wires, is transfer molded with resin, and the lead frame is used as a border in the envelope that leads the leads out of the sealing resin. 1. A semiconductor envelope for resin sealing, characterized in that an insulator layer extending over an annular sealing resin layer obtained by providing a space in the vicinity of the semiconductor element in a sealing resin layer laminated on the semiconductor element is sealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60237513A JPS6298751A (en) | 1985-10-25 | 1985-10-25 | Semiconductor enclosure for resin sealing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60237513A JPS6298751A (en) | 1985-10-25 | 1985-10-25 | Semiconductor enclosure for resin sealing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6298751A true JPS6298751A (en) | 1987-05-08 |
Family
ID=17016434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60237513A Pending JPS6298751A (en) | 1985-10-25 | 1985-10-25 | Semiconductor enclosure for resin sealing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6298751A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09213826A (en) * | 1996-02-01 | 1997-08-15 | Nec Corp | Package |
| EP1263042A1 (en) * | 2001-05-31 | 2002-12-04 | STMicroelectronics S.A. | Semiconductor package with recessed lead frame and recessed lead frame |
| FR2836281A1 (en) * | 2002-02-20 | 2003-08-22 | St Microelectronics Sa | Flat conducting grid for semiconductor case, comprises a perforated zone made so to form the radially elongated legs between a central platform and a peripheral part |
-
1985
- 1985-10-25 JP JP60237513A patent/JPS6298751A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09213826A (en) * | 1996-02-01 | 1997-08-15 | Nec Corp | Package |
| US5905301A (en) * | 1996-02-01 | 1999-05-18 | Nec Corporation | Mold package for sealing a chip |
| EP1263042A1 (en) * | 2001-05-31 | 2002-12-04 | STMicroelectronics S.A. | Semiconductor package with recessed lead frame and recessed lead frame |
| FR2825515A1 (en) * | 2001-05-31 | 2002-12-06 | St Microelectronics Sa | SEMICONDUCTOR PACKAGE WITH HOLLOW GRID AND HOLLOW GRID |
| US6838752B2 (en) | 2001-05-31 | 2005-01-04 | Stmicroelectronics S.A. | Semiconductor package with recessed leadframe and a recessed leadframe |
| FR2836281A1 (en) * | 2002-02-20 | 2003-08-22 | St Microelectronics Sa | Flat conducting grid for semiconductor case, comprises a perforated zone made so to form the radially elongated legs between a central platform and a peripheral part |
| US6885088B2 (en) | 2002-02-20 | 2005-04-26 | Stmicroelectronics Sa | Flat leadframe for a semiconductor package |
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