JPH0661365A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lessen a package in high frequency loss by a method wherein the electrode pads of a pellet and the inner leads of a base are electrically and mechanically connected together with bumps. CONSTITUTION:An SHF band low-noise amplification FET 1 equipped with inner leads 3 which lead 2DEG-FET circuit of a pellet 2 out of the FET 1, bump connections 4 formed of hemispheric bumps which are made of solder material (Pb/Sn) and fused between the electrode pads of the pellet 2 and the inner leads 3 to connect them electrically and mechanically, and a ceramic package. Furthermore, outer leads are bonded to the outer side of the package 5 through the intermediary of a metallized layer. As the electrode pads of a pellet and the inner leads of a base can be lessened in inductance between them and a package can be lessened in high frequency loss, a semiconductor device can be effectively lessened in NF as a whole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to gallium-arsenic (Ga).
As) The present invention relates to a semiconductor technology in which a pellet made of a semiconductor substrate (hereinafter referred to as a pellet) is used, and more particularly to a technology for reducing high frequency loss.
High Frequency. Hereinafter referred to as SHF. ) Band low-noise amplification field effect transistor (hereinafter referred to as S
It is called HF band low noise amplification FET. ) Related to effective technology.

[0002]

2. Description of the Related Art As an example of using a SHF band low noise amplifying FET, a satellite broadcast (Direct Broadcast) is used.
ng by Satellite. Hereinafter referred to as DBS. ) A converter for reception is included. SHF band low noise amplification FET used in this DBS reception converter
The two-dimensional electron gas field effect transistor (2 Dimensional Electron)
n GaAs Field Effect Transi
store. Hereinafter referred to as 2DEG-FET. ), There is.

As this 2DEG-FET,
A type in which -FET pellets are mounted in an ultra-small ceramic package and a type in which 2DEG-FET pellets are mounted in a resin mold package by transfer molding have been put into practical use.

Ceramic package type 2DEG-
FET is used when low noise, high gain and high performance are required, and it is a resin mold package type 2DEG.
The FET is used as a low-priced version or for interstage high frequency amplification of a DBS receiving converter.

A ceramic package type 2D
An example of the EG-FET is the Japan Electronic Industries Association (EIA).
J) registered model number, 2SK1615, 2SK1845,
There is. Also, resin mold package type 2D
As an example of EG-FET, 2SK1617,
There is 2SK1845.

Further, as an example in which such a 2DEG-FET is described, there is JP-A-1-132130.

By the way, the noise factor (hereinafter referred to as NF) which is the most important characteristic of the SHF band low noise amplification FET used in the DBS receiving converter has a high frequency loss in the NF of the FET pellet body and the high frequency loss of the package. The sum of the deterioration amount of NF and the deterioration amount of NF becomes the nominal characteristic of the SHF band low noise amplification FET. And this nominal characteristic NF
Is expressed by the following equation.

NF = NF of FET operating part + input loss + output loss / gain ...

In the formula, the NF of the FET operating portion corresponds to the NF of the FET pellet main body portion, and the NF of the input loss + output loss portion corresponds to the high frequency loss NF of the package portion.

Conventionally, for the purpose of reducing the NF, semiconductor manufacturers have focused on improving the NF of the FET operating section. For example, to improve the electron mobility of semiconductors,
We are evolving from a silicon FET structure to a GaAs-MESFET structure and then to a 2DEG-FET structure.

Further, in order to shorten the electron transfer time, each semiconductor manufacturer is working on miniaturization of the gate length, and at present, a mass production technology for ultra-fine processing of about 0.15 μm or less is established.

On the other hand, N due to high frequency loss of the package part
As a measure for reducing the deterioration of F, an ultra-small ceramic package is used for the purpose of reducing lead inductance and interelectrode capacitance. With the adoption of the ceramic package, the bonding wire length has been shortened to about 0.5 mm as much as possible, and a plurality of parallel wire bonding techniques have been implemented.

As a result, the inductance is reduced and the area of the electrode portion of the package is reduced as much as possible. Furthermore, the reduction of the interelectrode capacitance is ensured by minimizing the dielectric constant due to the hollow structure of the ceramic package.

On the other hand, since the package portion of the resin mold package type SHF band low noise amplifying FET intended for a low-priced version has an increased dielectric constant due to the filled resin material,
The high frequency loss of the package increases accordingly.

However, due to the devise of the lead frame shape, the input / output capacitance is smaller than that of the ceramic package type. A non-magnetic lead frame material (copper-based material) is used as a measure for reducing the lead inductance.

However, the resin mold type is still inferior in NF to the case where the same pellet is mounted on the ceramic package.

[0017]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As mentioned above, SH
The high performance of the F band low noise amplification FET by reducing the NF has heretofore been performed mainly by improving the NF of the FET operating section. However, in the SHF band low noise amplification FET, since the NF value at 12 GHz is around 0.5 dB as a boundary, it becomes disadvantageous in the NF improvement technology of the FET operation part, so a measure for reducing the high frequency loss NF of the package part is taken. The present inventor has revealed that this is more effective than taking measures to reduce the NF of the FET operating unit.

An object of the present invention is to provide a semiconductor device capable of reducing the high frequency loss of the package portion that contributes to the reduction of the high frequency noise figure, and a method of manufacturing the same.

A second object of the present invention is to provide a resin mold package type SHF band low noise amplifying FET of higher performance, paying attention to the cost merit of the resin mold package product.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0021]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, a semiconductor pellet in which a transistor circuit used in a high frequency band is built, and a plurality of wires which are wired outside the semiconductor pellet and are electrically connected to respective electrode pads of the semiconductor pellet. Inner leads and a package for encapsulating a semiconductor pellet and an inner lead group, wherein the inner lead group is metallized on the base of the package, the semiconductor pellet being the base, the semiconductor pellet Are electrically and mechanically connected by bump connecting portions formed between the electrode pads and the inner leads.

Further, the semiconductor pellets and the inner lead group are resin-sealed by a resin potted on the base.

[0024]

According to the above-mentioned first means, since the bonding wire is eliminated, the inductance due to the length of the bonding wire can be reduced. As a result, it is possible to reduce the high frequency loss of the package part,
The NF value of the entire semiconductor device can be reduced.

Further, according to the above-mentioned second means, even though the resin mold package type is used, it is possible to reduce the high frequency loss caused by the resin material around the bonding wire by making it wireless. , NF value can be reduced extremely effectively.

[0026]

1 is a vertical sectional view showing an SHF band low noise amplifying FET according to an embodiment of the present invention, FIG. 2 is a plan sectional view taken along the line II--II of FIG. 1, and FIG. 3 is used therefor. FIG. 4 is a vertical cross-sectional view showing a pellet having a pellet.
FIG. 5 and subsequent drawings are explanatory views showing a method of manufacturing an SHF band low noise amplification FET according to an embodiment of the present invention.

In this embodiment, the semiconductor device according to the present invention is constructed as an SHF band low noise amplifying FET 1. This SHF band low noise amplifying FET 1 has a pellet 2 configured as shown in FIGS. 3 and 4.
And a plurality of inner leads 3 for electrically pulling out the 2DEG-FET circuit built in the pellet 2 to the outside.
And a bump formed in a hemispherical shape using a solder material (Pb / Sn) is welded between the electrode pad of the pellet 2 and each inner lead 3 to electrically and mechanically connect the two. And the bump connecting portion 4 which is formed of ceramics so as to form an airtight chamber and hermetically seals the pellet, each inner lead and the bump connecting portion 4, and the ceramic package 5. It is provided with a plurality of outer leads that are electrically bonded to the inner leads 3 by being bonded to the outer surface of the inner leads 3 through a metallization layer, and are manufactured by a manufacturing method described later.

Pellets 2 shown in FIGS. 3 and 4.
Is 2DEG- in the state of a GaAs semiconductor substrate (wafer).
The FET circuit is manufactured and then individually separated.

As shown in FIG. 4, pellet 2
Is a two-dimensional gas forming layer 12 having a GaAs substrate 11 and an undoped layer 12a and a two-dimensional electron gas layer 12b formed by GaAs epitaxial growth.
, A two-dimensional electron gas supply layer 13, a contact layer 14, a source 15 made of Au.Ge/Ni/Au, a drain 16 and a gate 1 made of Al.
7, a first protective film (first passivation film) 18 made of phosphorus silicate glass (PSG) and SiO ₂ ,
An electric wiring layer 19 made of an Au-based material and a second protective film (second passivation film) 20 made of P-SiN (plasma-silicon nitride) are provided.

Further, as shown in FIG. 3, the pellet 2 includes a pair of source electrode pads 21, a single drain electrode pad 22, and a pair of gate electrode pads 2.
Equipped with 3. These electrode pads 21, 22 and 2
3 is electrically connected to the source 15, the drain 16 and the gate 17 through the wiring layer 19 (FIG. 4).
reference).

As shown in FIG. 3, the pair of source electrode pads 21, 21 are each formed in a substantially home-base shape, and face each other near the pair of end sides of the pellet 2. Each is arranged.

Further, the single drain electrode pad 22 is formed in a substantially square shape, and is arranged at a substantially central position on the side opposite to the gate electrode pad 23 of the line connecting both source electrode pads 21 and 21. It is set up.

Further, a pair of gate electrode pads 23,
23 are each formed in a substantially square shape, and are arranged on the opposite side of the drain electrode pad 22 with the gate 17 in between so as to be aligned with each other and with respect to the source electrode pad 21 at appropriate intervals. ing.

Then, as shown in FIGS. 3 and 4, the source electrode pad 21, the drain electrode pad 22 and the source electrode pad 23 have respective source solder bumps 24 and drain solder bumps 25. And each of the gate solder bumps 26 is formed in a substantially hemispherical shape. For example, each solder bump has a Pb of 95.
%, Sn is 5%, and is formed by a screen printing method or the like.

Next, a method of manufacturing the SHF band low noise amplifying FET according to one embodiment of the present invention will be described in the case where the pellet having the above-mentioned structure is used. Then, from this description, the details of the configuration of the SHF band low noise amplification FET 1 will be clarified at the same time.

SHF band low noise amplifying F according to the present embodiment
The multiple lead frame shown in FIGS. 5 to 7 is used in the method of manufacturing the ET.

The multiple lead frame 30 is made of Kovar having a small difference in coefficient of thermal expansion from ceramics, and is formed into a substantially rectangular frame plate shape by an appropriate means such as punching press working, and the surface thereof is formed. An Au plating film is deposited.

As shown in FIG. 5, the multiple lead frame 30 includes a plurality of unit lead frames 31, and each unit lead frame 31 is arranged in a horizontal row so that the same pattern is repeated in one direction. They are lined up and arranged in a row.

The unit lead frame 31 is provided with an outer frame 32 formed in a substantially square frame plate shape.
Is substantially shared between the adjacent unit lead frames 31.

On one diagonal of the outer frame 32, a pair of outer leads 33 for the source are arranged in a straight line so as to project so as to face each other, and on the other diagonal of the outer frame 32 for the drain. The outer leads 34 and the outer leads 35 for gates are arranged in a straight line, and electrically insulated gaps are respectively interposed at the intersections with the outer leads 33, 33 for sources, and they are integrally projected from both corners. It is set up. Both of the source outer leads 33, 33 are set wider than the drain outer leads 34 and the gate outer leads 35.

In FIG. 5, reference numerals 36 and 37 are through holes and notches for positioning.

A hermetically sealed package 5 is capped on the unit lead frame 31 (described later) and a sleeve 42.
A base 41 is formed on the central portion of each outer lead 33, 34, 35 for cooperation with the silver brazing portion 4 to form a base 41.
It is fixed via 0 (described later).

The base 41 is made of ceramic and is formed into an octagonal flat plate shape.
A source inner lead 43, a drain inner lead 44, and a gate inner lead 45, each of which is formed by depositing a gold (Au) plating layer on a base layer of tungsten (W), are metallized on the upper surface of the. ing. The inner leads 43, 44, 45 are printed on the upper surface of the base 41 by printing conductor patterns on the green sheet of the base 41.
It is formed by being performed over the side surface and the lower surface.

The sleeve 42 is made of ceramic, has an octagonal outer shape, and is formed in a cylindrical shape with both ends having a circular inner shape, and is concentrically arranged on the upper surface of the base 41 to be integrated. There is. The encapsulating material layer 4 made of a gold-tin (Au-Sn) alloy is formed on the upper opening end surface of the sleeve 42.
6 is applied by a suitable means such as a metallizing method. That is, the sleeve 42 is integrated in a completely joined state by performing conductor printing on the upper surface in a green sheet state, press-bonding it on the base 41, and firing it together with the base 41.

As shown in FIG. 6, the inner lead for source 43 is arranged on the center line of the sleeve 42 on the upper surface of the base 41 so that its width becomes narrow at the center and is interrupted halfway. Has been formed. The outer ends of the source inner leads 43 extend through the pair of opposite side walls of the sleeve 42 on the base 41 and extend to the back surface of the base 41. As shown in FIG. 7, both extension ends of the source inner leads 43 on the back surface of the base 41 are formed by the source outer leads 3 in the unit lead frame 31.
Metallized layers 53, 53 for mechanically and electrically connecting to 3, 33 respectively substantially constitute.

The inner lead 44 for drain is the base 41
On the center line of the sleeve 42 in the above, they are arranged on one side of the source inner lead 43, respectively, and face each other with an insulating gap at the tip. The outer end portion of the drain inner lead 44 penetrates the side wall of the sleeve 42 on the base 41 and extends to the back surface of the base 41. The extension of the drain inner lead 44 on the back surface of the base 41 substantially constitutes a metallization layer 54 for mechanically and electrically connecting to the drain outer lead 34 of the unit lead frame 31.

The gate inner leads 45 are arranged on one side of the source inner leads 43 on the center line of the sleeve 42 in the base 41, and face each other with an insulating gap at the tip. Inner lead for gate 45
The outer end of the base 41 penetrates the side wall of the sleeve 42 on the base 41 and extends to the back surface of the base 41.
The extension portion of the gate inner lead 45 on the back surface of the base 41 substantially constitutes a gate metallization layer 55 for mechanically and electrically connecting to the gate outer lead 35 in the unit lead frame 31.

Then, each metallized layer 53, 54, 55
A silver brazing material (not shown) for silver brazing is applied to each. The base 41 configured as described above includes the outer leads 33, 34 of the unit lead frame 31,
Each metallized layer 53, 54, 55 is placed on the concentrated portion 35 corresponding to the above-mentioned predetermined outer leads 33, 34, 35, and is passed through a heating furnace. Is given.

By this silver brazing treatment, after the wax material previously applied to the metallized layers 53, 54, 55 of the base 41 is melted, it is cooled and solidified. Silver brazing portions 40 are formed between the outer leads 33, 34 and 35, respectively. Then, by the silver brazing part 40, the source metallized layer 5
3, the source outer lead 33, the drain metallization layer 54, the drain outer lead 34, the gate metallization layer 55, and the source outer lead 35 are mechanically and electrically connected to each other, so that the base 41 is placed on the unit lead frame 31. It becomes stuck.

Then, in the state where the base 41 is fixed on the unit lead frame 31, the source inner lead 43 is the source outer lead 33, the drain inner lead 44 is the drain outer lead 34, and the gate inner lead 45 is the same. The gate outer leads 35 are electrically connected through the metallized layers 53, 54, 55, respectively.

In the multiple lead frame 30 as the work thus constructed, the pellet 2 according to the above construction is used in the gang bonding step as shown in FIG. Are gang-bonded to the inner leads 43, 44, 45 by the solder bumps 24, 25, 26, respectively.

That is, in the multiple lead frame 30 which is one work in the gang bonding process,
Solder paste (not shown) is applied to each inner lead 43, 4
4 and 45 are applied in advance by an appropriate means such as an application method using a dispenser. As the solder paste, for example, a solder paste material having Pb = 95% and Sn = 5% is used.

As described above, in the bump forming process,
Each of the solder bumps 2 on the pellet 2 which is the other work
4, 25, and 26 are arranged on the electrode pads 21, 22, and 23 and are provided in advance in a substantially hemispherical shape.

Then, in the gang bonding step, the pellet 2 is placed downward on the base 41 of each unit lead frame 31 of the multiple lead frame 30. At this time, the source solder bumps 24 of the pellet 2
And the source inner lead 43 of the base 41, the drain solder bump 25 and the drain inner lead 44, and the gate solder bump 26 and the gate inner lead 45 are arranged so as to be aligned with each other. Each solder bump 24, while being placed in this manner,
Since 25 and 26 are kept in the viscosity of the solder paste applied on the inner leads 43, 44 and 45, the pellet 2 is temporarily fixed to the base 1.

In this temporarily fixed state, the multiple lead frame 30 in which the pellets 2 are combined with the bases 41 is placed on a heat block (not shown), and the melting temperature (about 40
(0 ° C) or higher. Due to this heating, the solder bumps 24, 25, and 26 are transferred to the electrode pads 2 of the pellet 2.
It melts between 1, 22 and 23 and each inner lead 43, 44 and 45, respectively, and then cools and solidifies.

By melting and solidifying the solder bumps 24, 25, 26, bump connection portions 4 are formed between the electrode pads 21, 22, 23 and the inner leads 43, 44, 45, respectively. During this period, they are in a welded state. Therefore, the pellet 2 is electrically and mechanically gang-bonded to the inner leads 43, 44, 45 of the base 1.

During soldering in the gang bonding operation, when the solder bumps are melted and solidified, a self-alignment action due to surface tension works, so that each electrode pad 21, 22, 23 on the pellet 2 side and the base 41 side. The positional accuracy between the inner leads 43, 44, and 45 is automatically secured.

The multiple lead frame 30 as a work on which the gang bonding work has been performed as described above.
In the package molding process, a hermetically sealed package is formed as shown in FIG.

That is, as shown in FIG.
The cap 47 made of ceramic and formed in a cap shape corresponding to the sleeve 42 is
Over the encapsulant layer 46 formed on the upper end surface of the.

The ceramic cap 47 shown in FIG. 10 has a planar outer shape of the ceramic sleeve 42.
It is formed in a circular flat plate shape circumscribing the outer shape of the above, and a recess 48 is formed in the lower end surface in the shape of a circular hole having a constant depth. A metallized layer 49 is formed in an annular shape on the end surface adjacent to the recess of the cap 42. For example, the metallized layer 49 is formed by applying Au-Sn solder material containing 80% by weight of Au in a ring shape with a thickness of about 50 μm by thermocompression bonding after Au plating.

Then, the multiple lead frame 30 is placed on a heat block (not shown) with the cap 47 covering the sleeve 42, and is heated to about 320.degree. With this heating, the metallized layer 4 of the cap 47
9 is pressed against the encapsulant layer 46 on the top surface of the ceramic sleeve 42 and an appropriate vibration is applied. When the solder material is melted by this heating, pressing, and vibration, the cap 47 is welded to the sleeve 42 by the sealing material layer 46, so that the gap between the cap 47 and the sleeve 42 is sealed.

Next, in the cutting step, the multiple lead frame 30 in which the hermetically sealed package 5 is formed as described above is cut with a cutting die and a press to connect the outer leads 33, 34, 35 to predetermined leads. Cut to length. Along with this disconnection, the multiple lead frame 30 is divided into individual SHF band low noise amplifying FETs 1. At this time, the length of each outer lead is preferably 6 mm or more in order to facilitate the measurement of high frequency characteristics.

Then, in the sorting step, a predetermined SHF
By the measurement of the electrical characteristics (AC / DC) of the low-noise amplification FET 1 based on the product standard, the selection inspection of non-defective products and the appearance inspection and the like are performed.

Next, in the packing step, packing processing such as magazine packing and taping packing is carried out in accordance with the customer's request, and the final shipping form is obtained. Before packaging, the lead may be cut to a lead length necessary for the customer, if necessary.

As shown in FIG. 11, this SHF
The low-noise amplification FET 1 is mounted on the surface of a printed wiring board 60 for constructing a satellite broadcasting amplifier, and each outer lead is mechanically and electrically connected by reflow soldering, It is so-called surface mounted.

According to the above embodiment, the following effects can be obtained. In the conventional SHF band low noise amplification FET, the electrical connection between each electrode pad of the pellet and each inner lead of the base is about 0.5 to 0.8 mm, and
Although the thickness is about 20 μm, the SHF band low noise amplification FET according to the present embodiment has a height and a diameter of about 10 to 50 μm between each electrode pad and the inner lead. Since it is possible to reduce the inductance between each electrode pad of the pellet and each inner lead of the base by being connected by the solder bump connection part of, the high frequency loss in the package part can be reduced for both the input circuit and the output circuit. As a result, the SHF band low noise amplification FET can be reduced.
The overall NF can be reduced very effectively.

By electrically and mechanically gang-bonding the pellet and the base with the bump connecting portion group, the workability of connection can be improved as compared with the case of connecting by wire bonding.

In the SHF band low noise amplifying FET, by forming two solder bump connecting portions on each of the source and the gate, increasing the amount of electricity flowing between the electrode pad and the inner lead at the source and the gate. Therefore, the power can be sufficiently increased.

FIG. 12 is a bottom view showing a pellet used in the SHF band low noise amplifying FET according to the second embodiment of the present invention.

The second embodiment differs from the first embodiment in that
Two source electrode pads 21A, 21 of the pellet 2A
The position A is offset by a dimension A on the side of the drain electrode pad 22A.

According to the second embodiment, the parasitic capacitance between the source electrode pad 21A and the gate electrode pad 23A can be reduced. Therefore, in the SHF band low noise amplification FET, the package portion The NF can be further reduced.

FIG. 13 is a vertical sectional view showing an SHF band low noise amplifying FET according to a third embodiment of the present invention.

The third embodiment differs from the first embodiment in that
Silicon oil 61 is filled inside the hermetically sealed package 5, and the pellet 2, the inner lead 3 group, and the bump connecting portion 4 group are immersed in the silicon oil 61.

According to the third embodiment, the heat generated by the pellet 2 is radiated to the silicon oil 61, so that the heat radiation performance can be improved.

FIG. 14 is a vertical sectional view showing an SHF band low noise amplifying FET according to a fourth embodiment of the present invention.

The difference of the fourth embodiment from the first embodiment is that
A heat sink 62 is bonded to the pellet 2 by a bonding layer 63, and the pellet 2 and the heat sink 62 bonded to each other are immersed in the silicone oil 61 filled in the hermetically sealed package 5.
It is in.

According to the fourth embodiment, the heat generated by the pellet 2 is effectively dissipated to the silicon oil 61 by the heat sink 62 and further propagated to the outer shell of the hermetically sealed package 5 through the silicon oil 61. Very good heat dissipation performance.

FIG. 15 is a vertical sectional view showing an SHF band low noise amplifying FET according to a fifth embodiment of the present invention.

The difference of the fifth embodiment from the first embodiment is that
Instead of being hermetically sealed by the hermetically sealed package 5, the pellets 2 and the like are resin-sealed on the base 41 by a resin-sealed package 5A made of potting resin.

According to the fifth embodiment, the package can be formed in a small size and the manufacturing cost can be greatly reduced.

Further, since each electrode pad of the pellet 2 and each inner lead 3 of the base 41 are electrically connected by the bump connecting portion 4, the bump connecting portion 4 and the resin of the resin sealing package 5A are electrically connected to each other. It is possible to reduce the parasitic capacitance between them.

FIG. 16 is a vertical sectional view showing an SHF band low noise amplifying FET according to a sixth embodiment of the present invention.

The sixth embodiment differs from the first embodiment in that
The package is formed by a resin-sealed package 5B made of potting resin, and this resin-sealed package 5B is formed by filling a potting resin in a hole 64 on the bottom surface of the base 41B.

According to the sixth embodiment, the same effect as the fifth embodiment can be obtained.

In Examples 5 and 6 described above, by using a resin material having a low dielectric constant such as poly-tetra-fluoro-ethylene resin or poly-phenylene-ether resin as the potting resin, further It is possible to reduce noise.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the solder bumps for forming the bump connecting portions are not limited to be arranged on the pellet side, but may be arranged on the base side.

Further, the material of the bump for forming the bump connecting portion is not limited to the solder material, and other conductive material may be used.

In the above description, the SHF which is the field of application of the invention mainly made by the present inventor was the background.
The case where the present invention is applied to the manufacturing technology of the FET for low band noise amplification has been described.
Other applications of FE with pellets of s semiconductor
It can be applied to all manufacturing techniques for semiconductor devices such as T and integrated circuit devices (ICs).

[0090]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

By electrically and mechanically connecting each electrode pad of the pellet and each inner lead of the base by a bump connecting portion, an inductance between each electrode pad of the pellet and each inner lead of the base is formed. Therefore, the high frequency loss in the package portion can be reduced, and as a result, the NF of the entire semiconductor device can be reduced extremely effectively.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing an SHF band low noise amplification FET according to an embodiment of the present invention.

FIG. 2 is a plan sectional view taken along the line II-II of FIG.

FIG. 3 is a plan view showing a pellet used in the pellet.

FIG. 4 is a vertical sectional view thereof.

FIG. 5 is a FE for SHF band low noise amplification shown in FIG.
It is a partially omitted plan view showing a multiple lead frame used for manufacturing T.

6 is an enlarged partial plan view showing a VI portion of FIG.

FIG. 7 is an enlarged vertical sectional view thereof.

FIG. 8 is an enlarged vertical sectional view showing a state of gang bonding.

FIG. 9 is a SHF band low noise amplification FE shown in FIG.
It is a partial cutting disassembled front view which shows the sealing process in the manufacturing method of T.

FIG. 10 shows the cap used for it,
(A) is a longitudinal sectional view and (b) is a bottom view.

11 is an SHF band low noise amplifying F shown in FIG.
It is a perspective view which shows the mounting state of ET.

FIG. 12 is a bottom view showing a pellet used in the SHF band low noise amplification FET according to the second embodiment of the present invention.

FIG. 13 is a vertical cross-sectional view showing an SHF band low noise amplification FET according to a third embodiment of the present invention.

FIG. 14 is a vertical sectional view showing an SHF band low noise amplification FET according to a fourth embodiment of the present invention.

FIG. 15 is a vertical cross-sectional view showing an SHF band low noise amplification FET according to a fifth embodiment of the present invention.

FIG. 16 is a vertical cross-sectional view showing an SHF band low noise amplification FET according to a sixth embodiment of the present invention.

[Explanation of Codes] 1 ... GaAs FET (semiconductor device), 2 ... GaAs semiconductor pellet, 3 ... inner lead, 4 ... bump connection part,
5 ... Hermetically sealed package, 11 ... GaAs substrate part, 12
... two-dimensional electron gas forming layer, 12a ... undoped layer, 1
2b ... two-dimensional gas layer, 13 ... two-dimensional electron gas supply layer, 1
4 ... Contact layer, 15 ... Source, 16 ... Drain, 1
Reference numeral 7 ... Gate, 18 ... First holding film (first passivation film), 19 ... Wiring layer, 20 ... Second protective film (second passivation film), 21 ... Source electrode pad, 22 ... Drain electrode pad, 23 ... Gate electrode pad, 24 ...
Source solder bump, 25 ... Drain solder bump, 26 ... Gate solder bump, 30 ... Multiple lead frame, 31 ... Unit lead frame, 32 ... Outer frame, 33
... source outer lead, 34 ... drain outer lead, 35 ... gate outer lead, 36 ... positioning through hole, 37 ... positioning notch, 40 ... silver brazing part, 41
... base, 42 ... sleeve, 43 ... source inner lead, 44 ... drain inner lead, 45 ... gate inner lead, 46 ... encapsulating material layer, 47 ... cap, 48 ...
Recesses, 49 ... Metallization layer, 53 ... Source metallization layer, 54 ... Drain metallization layer, 55 ... Gate metallization layer, 60 ... Printed wiring board, 61 ... Silicon oil, 62 ... Heat sink, 63 ... Bonding layer,
64 ... hole.

Claims (6)

[Claims] 1. A semiconductor pellet in which a transistor circuit used in a high frequency band is built, and a plurality of wires which are wired outside the semiconductor pellet and are electrically connected to respective electrode pads of the semiconductor pellet. Inner leads and a package for encapsulating a semiconductor pellet and an inner lead group, in a semiconductor device in which the inner lead group is metallized on the base of the package, the semiconductor pellet on the base, the semiconductor pellet The semiconductor device is electrically and mechanically connected by a bump connecting portion formed between each of the electrode pads and each of the inner leads. 2. The semiconductor device according to claim 1, wherein the semiconductor pellet and the inner lead group are hermetically sealed by a hermetically sealed package. 3. The semiconductor device according to claim 1, wherein the semiconductor pellet and the inner lead group are resin-sealed with a resin potted to the base. 4. The semiconductor pellet is formed of a gallium-arsenic semiconductor substrate in which a two-dimensional electron gas field effect transistor circuit used in the centimeter wave band is formed, and the base of the package is formed of ceramic. The inner leads are formed by printing a conductor pattern on the ceramic base, and the bump connecting portions are solders formed on the source electrode pad, the drain electrode pad and the gate electrode pad of the semiconductor pellet, respectively. The semiconductor device according to claim 1, wherein the bump is formed by melting and then solidifying. 5. The semiconductor device according to claim 4, wherein the position of the source electrode pad is offset to the drain electrode pad side. 6. The method of manufacturing a semiconductor device according to claim 1, wherein a bump forming step in which bumps are formed on each electrode pad of the semiconductor pellet, and the semiconductor pellet in which the bump group is formed is the bump. On the base, the bumps are melted and then solidified after the bumps are melted in a state in which the bumps are melted in a state in which the bumps are melted in a state in which the bumps are melted in a state in which the bumps are melted in a state in which the bumps are melted in a state in which the bumps are melted in a state in which the bumps are melted in a state in which the bumps are melted, respectively. And a step of forming a bump connecting portion between each electrode pad and each inner lead, respectively.