CA2011518A1 - Puces de memoire vive dynamique avec antememoire repartie et methode de controle connexe - Google Patents

Puces de memoire vive dynamique avec antememoire repartie et methode de controle connexe

Info

Publication number
CA2011518A1
CA2011518A1 CA2011518A CA2011518A CA2011518A1 CA 2011518 A1 CA2011518 A1 CA 2011518A1 CA 2011518 A CA2011518 A CA 2011518A CA 2011518 A CA2011518 A CA 2011518A CA 2011518 A1 CA2011518 A1 CA 2011518A1
Authority
CA
Canada
Prior art keywords
sram
chip
multiplexor
dram
distributed cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2011518A
Other languages
English (en)
Other versions
CA2011518C (fr
Inventor
Ronald N. Fortino
Harry I. Linzer
Kim E. O'donnell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2011518A1 publication Critical patent/CA2011518A1/fr
Application granted granted Critical
Publication of CA2011518C publication Critical patent/CA2011518C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
  • Memory System (AREA)
CA002011518A 1989-04-25 1990-03-05 Puces de memoire vive dynamique avec antememoire repartie et methode de controle connexe Expired - Fee Related CA2011518C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34283389A 1989-04-25 1989-04-25
US342,833 1989-04-25

Publications (2)

Publication Number Publication Date
CA2011518A1 true CA2011518A1 (fr) 1990-10-25
CA2011518C CA2011518C (fr) 1993-04-20

Family

ID=23343468

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002011518A Expired - Fee Related CA2011518C (fr) 1989-04-25 1990-03-05 Puces de memoire vive dynamique avec antememoire repartie et methode de controle connexe

Country Status (4)

Country Link
US (1) US5421000A (fr)
EP (1) EP0395559A3 (fr)
JP (1) JPH0652633B2 (fr)
CA (1) CA2011518C (fr)

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US5898856A (en) * 1995-09-15 1999-04-27 Intel Corporation Method and apparatus for automatically detecting a selected cache type
US5835941A (en) * 1995-11-17 1998-11-10 Micron Technology Inc. Internally cached static random access memory architecture
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US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US6404670B2 (en) 1996-05-24 2002-06-11 Uniram Technology, Inc. Multiple ports memory-cell structure
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US6167486A (en) * 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5963481A (en) * 1998-06-30 1999-10-05 Enhanced Memory Systems, Inc. Embedded enhanced DRAM, and associated method
US6249840B1 (en) * 1998-10-23 2001-06-19 Enhanced Memory Systems, Inc. Multi-bank ESDRAM with cross-coupled SRAM cache registers
KR100280518B1 (ko) * 1998-11-10 2001-03-02 김영환 동기 에스램 회로
US6330636B1 (en) 1999-01-29 2001-12-11 Enhanced Memory Systems, Inc. Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank
US6101132A (en) * 1999-02-03 2000-08-08 Xilinx, Inc. Block RAM with reset
US6282127B1 (en) 1999-02-03 2001-08-28 Xilinx, Inc. Block RAM with reset to user selected value
US6094705A (en) * 1999-03-10 2000-07-25 Picoturbo, Inc. Method and system for selective DRAM refresh to reduce power consumption
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
JP3940539B2 (ja) 2000-02-03 2007-07-04 株式会社日立製作所 半導体集積回路
US6862654B1 (en) 2000-08-17 2005-03-01 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
US6496425B1 (en) * 2000-08-21 2002-12-17 Micron Technology, Inc Multiple bit line column redundancy
US6779076B1 (en) 2000-10-05 2004-08-17 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
US20020147884A1 (en) * 2001-04-05 2002-10-10 Michael Peters Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
KR100427723B1 (ko) * 2001-11-21 2004-04-28 주식회사 하이닉스반도체 메모리 서브시스템
US7117316B2 (en) 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7120727B2 (en) 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7330992B2 (en) 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US7341765B2 (en) * 2004-01-27 2008-03-11 Battelle Energy Alliance, Llc Metallic coatings on silicon substrates, and methods of forming metallic coatings on silicon substrates
US7188219B2 (en) 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US7308526B2 (en) * 2004-06-02 2007-12-11 Intel Corporation Memory controller module having independent memory controllers for different memory types
US7519788B2 (en) 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7466647B2 (en) * 2005-02-09 2008-12-16 International Business Machines Corporation Efficient muxing scheme to allow for bypass and array access
US20080090610A1 (en) * 2006-10-13 2008-04-17 Alpha Imaging Technology, R.O.C. Portable electronic device
JP4674865B2 (ja) * 2006-10-30 2011-04-20 株式会社日立製作所 半導体集積回路
US7584335B2 (en) 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage
TWI376672B (en) * 2007-06-21 2012-11-11 Novatek Microelectronics Corp Memory-control device for display device
US7729183B2 (en) * 2008-06-26 2010-06-01 Promos Technologies Inc. Data sensing method for dynamic random access memory
US8810589B1 (en) * 2009-11-12 2014-08-19 Marvell Israel (M.I.S.L) Ltd. Method and apparatus for refreshing display
US11593001B1 (en) * 2021-08-02 2023-02-28 Nvidia Corporation Using per memory bank load caches for reducing power use in a system on a chip

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US4616310A (en) * 1983-05-20 1986-10-07 International Business Machines Corporation Communicating random access memory
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US4691289A (en) * 1984-07-23 1987-09-01 Texas Instruments Incorporated State machine standard cell that supports both a Moore and a Mealy implementation
JPH0630075B2 (ja) * 1984-08-31 1994-04-20 株式会社日立製作所 キャッシュメモリを有するデータ処理装置
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
US4682284A (en) * 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access
US4713756A (en) * 1985-02-28 1987-12-15 Westinghouse Electric Corp. Non-volatile memory device for a programmable controller
US4701843A (en) * 1985-04-01 1987-10-20 Ncr Corporation Refresh system for a page addressable memory
US4755964A (en) * 1985-04-19 1988-07-05 American Telephone And Telegraph Company Memory control circuit permitting microcomputer system to utilize static and dynamic rams
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JPH087995B2 (ja) * 1985-08-16 1996-01-29 富士通株式会社 ダイナミツク半導体記憶装置のリフレツシユ方法および装置
JPH0736269B2 (ja) * 1985-08-30 1995-04-19 株式会社日立製作所 半導体記憶装置
JPS62103898A (ja) * 1985-10-31 1987-05-14 Mitsubishi Electric Corp ダイナミツクランダムアクセスメモリ装置
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JPS62149099A (ja) * 1985-12-23 1987-07-03 Toshiba Corp メモリアクセス制御回路
US4829471A (en) * 1986-02-07 1989-05-09 Advanced Micro Devices, Inc. Data load sequencer for multiple data line serializer
US4797850A (en) * 1986-05-12 1989-01-10 Advanced Micro Devices, Inc. Dynamic random access memory controller with multiple independent control channels
JPS62278651A (ja) * 1986-05-28 1987-12-03 Hitachi Ltd 部分書込制御装置
JPS6339057A (ja) * 1986-08-05 1988-02-19 Fujitsu Ltd 仮想記憶メモリ
US4800535A (en) * 1987-04-28 1989-01-24 Aptec Computer Systems, Inc. Interleaved memory addressing system and method using a parity signal
US4894770A (en) * 1987-06-01 1990-01-16 Massachusetts Institute Of Technology Set associative memory
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US4937791A (en) * 1988-06-02 1990-06-26 The California Institute Of Technology High performance dynamic ram interface

Also Published As

Publication number Publication date
EP0395559A2 (fr) 1990-10-31
EP0395559A3 (fr) 1992-06-03
JPH02297791A (ja) 1990-12-10
JPH0652633B2 (ja) 1994-07-06
CA2011518C (fr) 1993-04-20
US5421000A (en) 1995-05-30

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