CA2011103C - Apparatus for decoding bose-chanhuri-hocqueghem code for correcting complex errors - Google Patents
Apparatus for decoding bose-chanhuri-hocqueghem code for correcting complex errorsInfo
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- CA2011103C CA2011103C CA002011103A CA2011103A CA2011103C CA 2011103 C CA2011103 C CA 2011103C CA 002011103 A CA002011103 A CA 002011103A CA 2011103 A CA2011103 A CA 2011103A CA 2011103 C CA2011103 C CA 2011103C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/17—Burst error correction, e.g. error trapping, Fire codes
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- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
An apparatus for decoding a received BCH code signal for correcting a combined complex error is disclosed which includes a syndrome generating circuit for generating two n-bit syndromes corresponding to the received signal, a syndrome converting circuit for converting the two n-bit syndromes to a 2n-bit syndrome. a random error correcting circuit, a burst error correcting circuit, two combining circuits and output selecting circuit. The random error correcting circuit inputs the two n-bit syndromes and out-puts a random error correction signal to one of the combin-ing circuits and the burst error correcting circuit inputs the 2n-bit syndrome and outputs a burst error correction signal to the other of the combining circuits. The combin-ing circuits combine-the correction signals to the received BCH code signal. The output selecting circuit selectively outputs one of the combined signals from the combining circuits in accordance with the decoding conditions of the error correcting circuits and the result of comparison between the decoded and error-corrected signals from the combining circuits.
Description
-1- 201 1 ~03 APPARATUS FOR DECODING BOSE-CHANDHURI-HOCQUEGHEM CODE FOR CORRECTING COMPLEX ERRORS
Background of the Invention:
1. Field of the Invention S The present invention relates to a error correction apparatus in a digital communication system using a BCH
(Bose-Chandhuri-Hocqueghem) code, more particularly relates to a BCH code decoding apparatus for correcting a complex error in a digital communication system.
Background of the Invention:
1. Field of the Invention S The present invention relates to a error correction apparatus in a digital communication system using a BCH
(Bose-Chandhuri-Hocqueghem) code, more particularly relates to a BCH code decoding apparatus for correcting a complex error in a digital communication system.
2. Description of the Prior Art Fig. 1 is a block diagram showing a conventional combined-error-correcting circuit for correcting both random and burst errors, as described, for example, in "Error Control Coding: Fundamentals and Applications" by S. LIN
and D.J. COSTELL0, Jr., pp. 280 - 282, published from Prentice-Hall, Inc., 1983.- In the figure, numeral 1 is an input terminal for inputting a received coded message, 39 is a burst-error-correcting unit for correcting a burst error by burst trapping, 40 is a random-error-correcting unit for correcting a random error, 6 is an output selecting circuit for selecting either the output from the burst-error-correcting unit 39 or the output from the random-error-correcting unit 40 and 9 is an output terminal for outputting an decoded result.
The operation of the above-mentioned prior art will now be described. A received message which has been decoded at a transmltter site before transmitting and includes errors added in the communication path is input from the input terminal 1 into both of the burst-error-correcting unit 39 and the random-error-correcting unit 40. The message is decoded by the respective correcting units, and either the decoded output from the burst-error-correcting unit 39 or the decoded output from the random-error-correcting unit 40 is selected by the output selecting circuit 6 in response to the condition of the communication path, and thereby the selected output is delivered from the output terminal 9 as an output of the complex error correct-ing circuit.
Since conventional complex error correcting circuitsare generally arranged as described above, it is necessary to control the output selecting circuit 6 in response to the condition of the communication path with respect to the con-crete error correcting code, but there is shown no definitesuggestion as to how the condition of the communication path can be concretely grasped and there is also shown no crite-rion to appropriately judge such a condition, therefore it is difficult to accurately control the selecting circuit 6.
There is a further problem that, because of the burst error correcting unit and the random error correcting unit being independently arranged from each other, it is necessary that the respective units independently include syndrome gener-ating circuits for extracting the error condition.
Summary of the Invention:
It is an object of the present invention to solvesuch problems as described above and to obtain an apparatus for decoding a BCH code signal and for correcting a complex - ~3~ 201 1 103 error combined in the BCH code signal whlch is capable of grasping the condition of the communication path, concretely providing a criterion for ~udging the condition of the communication path and commonly using a syndrome generating s circuit for a burst error correcting unit and a random error correcting unit.
This ob~ect is achieved by an apparatus for decoding a BCH code used for correcting a complex error which is capable of grasping the condition of a communication path by using the decoded result of a burst error correcting unit with a burst trapping functlon as well as the decoded result of the random error correcting unit having a circuit for deciding the result of an operation with a circuit for making an operation of integers of modulo 2n-1, thereby concretely providing a criterion for ~udging the condition of the communication path to control an output selecting circuit and there being further provided a means for converting a syndrome. thereby the common use of a syndrome generating circuit can be attained.
Accordingly, one aspect of the present invention relates to an apparatus for decoding a received BCH code signal on a communication path for correcting complex error comprising:
a syndrome generating circuit for generating two syndromes for correcting a random error of said BcH code signal;
-3a- 201 1 1 03 a first unit for correcting a random error of said BCH
code signal by using decoding means, said first unit being connected to said syndrome generating circuit to receive and use the two syndromes in correcting the random error;
a syndrome converting circuit, connected to said syndrome generating circuit, for converting said two syndromes into a single converted syndrome;
a second unit for correcting a burst error of said BCH
code signal by using decoding means, said second unit being connected to said syndrome generating circuit to receive and use the converted syndrome in correcting the burst error; and a third unit connected to said first and second units for deciding which output signal of said first or second unit is to be selectively output in response to the condition of the 5 communication path, said third unit including means for grasping the condition of the communication path, said means connected to the first and second units to receive decoded output signals from said first and second units wherein the output signals are used to grasp 0 the condition of the communication path, and means for judging the condition of the communication path as obtained by the means for grasping to determine which output signal of said first and second units is to be selectively output.
In a further aspect, the present invention relates to an apparatus for decoding a received BCH code signal for correcting a combined complex error, the apparatus comprising:
_ -3b-a first unit for correcting a random error of said BCH
code signal by using decoding means to produce a first decoded output signal and a first decoding condition signal;
a second unit for correcting a burst error of said BCH
code signal by using decoding means to produce a second decoded output signal and a second decoding condition signal, wherein a decoding condition signal relates to an indication of correctable or uncorrectable error detection by the respective unit; and a third unit connected to said first and second units for selecting one of the decoded output signals based on a combination of the first and second decoding condition signals and the first and second decoded output signals, said third unit including means for receiving the decoded output signals from said first and second units, means for determining which output signal of said first and second units is to be selectively output, means for determining whether at least one of the first and second decoded output signals is a correctable error signal, and means for providing an uncorrectable error output signal in response to a determination that neither the first nor second decoded output signal is a correctable error signal.
In a still further aspect, the present invention relates to an apparatus for decoding a received BCH code signal for correcting a combined complex error, the apparatus ,-- . .
-3c-comprising:
a random error decoder for receiving the BCH code signal and for providing a first decoded output signal, and a first decoding condition signal;
a burst error decoder for receiving the BCH code signal and for providing a second decoded output signal, and a second decoding condition signal, the first and 10 second decoding condition signal being indications of an error correction or an error detection; and a selector including means for receiving the first and second decoded output signals and the first and second decoding condition 5 signals from the decoders, and means for selecting one of the first and second decoded output signals based on the received signals.
In a further aspect, the present invention relates to an apparatus for decoding a received BCH code signal for 20 correcting a combined comp-lex error, the apparatus comprising:
a random error decoder for receiving the BCH code signal and for providing a first decoded output signal;
a burst error decoder for receiving the BCH code signal and for providing a second decoded output signal, and an 25 uncorrectable error signal for indicating whether there is an uncorrectable error; and _ -3d- 20 1 1 1 03 a selector for receiving the first and second decoded output signals and the uncorrectable error signal and for selecting and outputting one of the first and second decoded output signals based on the received signals.
In a still further aspect, the present invention relates to a method for providing a decoded output signal from an input signal, the method including the steps of:
providing a first error corrector which receives the input signal and provides a first decoded output signal and a first decoding condition signal;
providing a second error corrector which receives the input signal and provides a second decoded output signal and a second decoding condition signal, wherein the first and second error correctors correct errors in a different manner;
receiving the first and second decoded output signals and the first and second decoding condition signals; and selecting one of the first and second decoded output signals in response to the received signals.
Brief Description of the Dra~ings:
Flg. 1 illustrates a block diagram showing a conven-tional apparatus for decoding a BCH code with a correctlon function oi a complex error;
Fig. 2 is a block diagram showing an apparatus for decoding a BCH code with a correction function of a complex error according to thls invention;
Fig. 3 is a block diagram showing details of the random error correcting circuit shown in Fig. 2;
20~ 1 ~ 0~
Flg. 4 is a detailed dlagram of the burst error correcting clrcuit shown ln Fig. 2;
Fig. 5 shows a detailed diagram of the output select-ing circuit illustrated ln Fig. 2; and Fig. 6 is a table showing the criterion for control-ling the output selecting switch incorporated in the output selection control circuit shown in Fig. 5.
Detailed Description of the Preferred Embodiments:
An embodlment of the present lnventlon wlll now be described. Referring now to Flg. 2, there ls shown ln block dlagram form a error correcting unlt. In the drawing, numeral 1 denotes an input terminal for inputting a coded message received, 2 a syndrome generating circuit for gener-ating two n-bit syndromes for correcting a random error, 3 a lS delay circuit for holding the received message during the period of generating the syndromes and correcting an error, 4 a syndrome converting circuit for performing a conversion from the two n-bit syndromes generated in the syndrome generating circuit 2 to a 2n-bit syndrome for a burst trapping circuit for correcting a burst error, 5 a burst error correcting circuit for calculating the posi-tion in which a burst error is generated, and the pattern of the burst error, 6 an output selectlng circuit incorporating a criterion for grasping and ~udging the condition of a communlcatlon path by uslng the decoded results of the burst error correcting circult 5 and a random error correctlng circuit mentioned next, 7 a random error correcting circuit for recelving, as an lnput, the syndrome which is vector C
-expressed by the polynomial basis in a finite field and obtained with the syndrome generating circuit 2, converting the syndrome vector-expressed syndrome to an exponential expression of a primitive element of the finite field, obtaining an error position polynomial by normalizing the converted exponential repression with an integer operation of modulo 2n-1, obtaining the radical of the normalized error position polynomial by looking up a table of the normalized error position pre-calculated the constant terms of the normalized error position polynomial, calculating the true error position from the normalized error position, and correcting the random error, 8 a data ROM for storing data for converting the syndrome vector-expressed by the poly-nomial basis in the finite field obtained by the syndrome generating circuit 2 into the exponential expression of the primitive element of the finite field and data of the norma-lized error position which is the radical of the normalized error position polynomial, 9 an output terminal for output-ting the decoded results, 10 a terminal for outputting a signal when a uncorrectable error showing the final decoded condition is detected, and ll-a and ll-b exclusive OR
circuits for adding error correction pulses output from the burst error and random error correcting circuits 5 and 7 to the received message.
Fig. 3 shows the details of the random error correct-ing circuit 7 shown in Fig. 2, and in this figure, numeral 12 is an input terminal for inputting the syndrome vector-expressed with the polynomial basis in the finite field _ -6- ~ 01 1 103 obtained by the syndrome ~enerating circuit 2 shown in Fig. 2, 13 a register for holding the input syndrome, 14 an adding circuit with modulo 2 -1, 15 .~
a complementary number circuit with modulo 2 -1, 16 a register for temporarily holding data, 17 a register having a function for checking the results of calculation by the adding circuit 14 with modulo 2n-1 and the complementary number circuit 15 with modulo 2n-1, 18 a counter circuit for calculating the true error position, 19 an OR circuit for mixlng the correction pulses output from the counter circuits 18 and 18, 20 an address control circuit for outputting an address to the data ROM 8 which stores the data for converting the syndrome vector-expressed with the polynomial basis in the finite field to the expo-nential expression of the primitive element of the finitefield and the data of the normalized error position which is a radical of the normalized error position polynomial, 21 an address terminal for outputting and address to the data ROM
8, 22 a data input terminal to which data are inputted from the data ROM 8, 23 an output terminal for outputting the correction pulse, and 24 a terminal for outputting a un-correctable error detection signal when an error which can not be corrected at the random error correcting circuit 7.
Fig. 4 shows the details of the burst error correct-ing circuit 5 shown in Fig. 2 in which numeral 25 is an input terminal for inputting the output of the syndrome converting circuit 4 illustrated in Fig. 2, 26 a l-bit delay circuit, 27 a switch for controlling a feedback circuit B
consisting of the delay circuits 26 connected in loop through the switch, 28 a selecting switch for selecting either the output from the syndrome converting circuit 4 or the data from the feedback circuit, 29 a trapping (zero detection) circuit for detecting the fact that the upper (2n-b)-bits of the linear feedback shift register, or the feedback circuit having 2n-bits in length become zero, 30 a terminal outputting a uncorrectable burst error detection signal when an error which can not be corrected at the burst error correcting circuit 5 is detected, and 31 an error-pattern output terminal for serially outputting an error-pattern to be corrected when the burst error is corrected.
Fig. 5 is a detailed block diagram of the output selecting circuit 6 shown in Fig. 2 including the criterion for grasping and judging the condition of the communication path by using the decoded results of the burst error and random error correcting circuits 5 and 7 shown in Fig. 2.
In Fig. 5, numeral 32 denotes an input terminal for the data which has been corrected by using the output from the random error correcting circuit 7, 33 an input terminal for data which has been corrected by using the output from the burst error correcting circuit 5, 34 an exclusive OR circuit for comparing the data corrected by the random error correcting circuit 7 and the data corrected by the burst error correct-ing circuit 5, 35 an input terminal of the uncorrectableerror detection signal from the terminal 24 related to the random error correcting circuit 7, 36 an input terminal of the uncorrectable error detection signal from the terminal 31 related to the burst error correcting circuit 5, 37 an output selecting switch for selecting either the data corrected by the random error correcting circuit 7 or the data corrected by the burst error correcting circuit 5, s and 38 an output selection control circuit for generating a uncorrectable signal to the terminal 10 (shown in Figs. 2 and 4) depending on the uncorrectable error detection signals input from the random and burst error correcting circuits 7 and 5 to the input terminals 35 and 36, and the generating a control signal for controlling the output selecting switch 37 in accordance with the error detection signals and the output signal from the exclusive OR circuit 34 which compares the data input to the terminal 32, which has been corrected by the random error correcting circuit 7 and the data input to the terminal 33, which has been corrected by the burst error correcting circuit 5.
Fig. 6 is a table showing the criterion for control-ling the output selecting switch 37 incorporated in the selecting circuit 6 and the criterion for deciding the uncorrectable error signal to the terminal 10.
The operation will now be described. A message which has been coded at a transmitter side and includes errors added at the communication path is received at the input terminal 1. Two n-bit syndromes S1, S3 expressed by vectors of the polynomial basis in the finite field is generated by the syndrome generating circuit 2. The two n-bit syndromes S 1, S3 are then input to the random error correcting circuit 7 and the syndrome converting circuit 4. In the random ~` 201 1 1 03 g error correcting circuit 7, the input syndromes Sl, S3 are held in the register 13 and output as address of the data ROM 8 through the address control circuit 20 to the address output terminal 21. The syndromes Sl, S3 are converted by the data ROM 8 from the vector expression with the polynomial basis in the finite field to the exponential expression of primitive element of finite field, log Sl and log S3 . The converted syndromes log Sl and log S3, are stored into the register 16 by way of the data input terminal 22 and the register 17. Based on the exponentially expressed syndromes log Sl and log S3 stored in the register 16, the constant term (log S3 - log Sl) of the normalized error position polynomial is calculated using the adding circuit 14 and the complementary number circuit 15, and the constant term (log S3 - 3 x log S1) is then output as address of the data ROM 8 through the address control circuit 20 and the address output terminal 21. The constant term (log S3 - 3 x log S1) is then converted by the data ROM 8 to two radicals i =
log ~i and j = log ~j of the normalized error position poly-nomial. Herein, ~ is a primitive element of finite field and ~i and ~i are radicals of the normalized error position polynomial, i.e., are represented the normalized error position. The two radicals i = log ~i and j = log ~j of the error position polynomial normalized by the data ROM 8 are directed through the data input terminal 22 and the register 17 and added by the adding circuit 14 with log S
and stored in the counter circuit 18 for calculating o- 2~ 3 the true error position. At this time, the result of addition is checked by the register 17, and if it is in a uncorrectable condition, a uncorrectable error detection signal is output to the terminal 24. The true error position stored in the counter circuit 18 is counted down, and when the content of the counter circuit 18 becomes zero, an error correction pulse is given through the OR
circuit 19 to the exclusive OR circuit ll-a.
On the other hand, the two n-bit syndromes S1 and S3 input into the syndrome converting circuit 4 are converted to 2n-bit syndromes and thereafter input to the burst error correcting circuit 5. For example, for (511, 493) BCH codes having the generated polynomial of:
g(x) = Xl8 + X15 + X12 + X10 + x8 + X7 + x6 + X3 + 1 the conversion is performed in accordance with the following equations:
Slo = Sl7 + Sl4 + Sl3 + Sl1- 1 + S37 + S34 + S33 + S31 Sl8 + S15 + S14 + Sl2 + Sll + Slo + S38 + S35 + S34 + S31 + S3O
2 S16 + S15 + Sl3 + S12 + Sl 1 + Slo + S36 + S3s + S33 + S31 + S3O
S13 = S16 + S12 + S36 + S33 + S32 S14 = Sl7 + Sl3 + S37 + S34 33 S15 = S18 + S14 + Slo + S38 + S3s 34 3 S16 = Sl7 + Sl5 + Sl4 + S13 S37 + S36 + S3s + S34 + S33 7 Sl8 + Sl7 + Sl6 + Sl5 + S13 + Sl r 3 36 35 S33 + S31 8 Sl8 + Sl6 + Sl3 + Sl2 + Sl1 + S1O
S36 + S33 + S32 + S31 + S3O
Sls = S17 + S14 + S13 + S1 S37 + S34 + S33 + S32 + S
Sll o = Sl8 + S17 + S15 +
S38 + S37 + S3s + S32 + S
Sll 1 = Sl8 + Sl6 + S13 + Sl2 1 S38 + S36 + S33 + S32 + S3O
S112 = S1O + S3O
Sll3 = Sll + S31 Sll4 = Sl2 + S32 Sl 1 s = Sl7 + Sl4 + Sl 1 + S10 + S37 + S34 + S31 + S3O
Sll6 Sl8 Sl5 Sl2 S
+ S38 + S3s + S32 + S
S1l7 = Sl6 + Sl3 + Sl2 + S1O
+ S36 + S33 + S32 + S3O
In the burst error correcting circuit 5, the switch 27 for controlling the feedback is closed and the selecting switches 28 are turned to the sides "a" connected to the input terminals 25 so that the two n-bit syndromes converted by the syndrome converting circuit 4 are inputted to the delay circuit 26 of the linear feedback shift register circuit having 2n-bit in length. The selecting switch 28 is then turned to the linear feedback shift register circuit sides "b" and the burst error pattern is checked by the trapping (zero detection) circuit 29 while performing the shifting operation. If the burst error pattern is detected If an error pattern is detected at the random error correcting circuit 7 or the burst error correcting circuit 5, the received message is read out from the delay circuit 3 in which the received message has been held, the respective error patterns detected at the random and burst error correcting clrcuits 7 and 5 are separately combined to the received message by the exclusive OR circuits ll-a, ll-b, and thus the random and burst errors are corrected to provide thelr decoded messages. Thereafter, the decoded messages corrected by the random error and burst error correcting circuits 7 and 5 and the outputs from the un-correctable error detectlon terminals 24, 30 connected to the random error and burst error correcting circuits 7 and 5 are input to the output selecting circuit 6. In the output selecting circuit 6, the respective messages input from the random error and burst error correcting clrcuits 7 and 5 are compared by the e~cluslve OR circuit 34. The result of com-parlson by the excluslve OR circuit 34 and the uncorrectableerror detectlon slgnals from the terminals 24, 30 are lnput to the output selection control clrcult 38 whlch, ln turn, controls the output selecting switch 37 in accordance wlth , ,, ' f' 201 1 1~
-the criterion of output selectlon shown ln Flg. 6. Thus, if both of the uncorrectable error detection signals from the terminals 24, 30 show the correction and the output of the exclusive OR circuit 34 which compares the respective decoded messages shows the decoded messages being identical, then the output selecting switch 37 is turned to its ~a~-side to select the output of the random error correcting circuit 7 through the exclusive OR circuit ll-a, and if the uncorrectable error detection signal from the terminal 24 shows correction and the uncorrectable error detection signal from the terminal 30 shows detection of any un-correctable error, the output selecting switch 37 is turned to its "a~-side to select the same output as the above, and if the uncorrectable error detectlon slgnal from the terminal 30 shows correctlon and the uncorrectable error detectlon slgnal from the terminal 24 shows detection of any uncorrectable error, then the output selectlng swltch 37 is turned to its "b~-side to select the output of the burst error correcting circuit 5 through the exclusive OR circuit ll-b, and in other cases, the signal which represents the existence of uncorrectable error is output at the terminal lO. The final decoded message selected by the output selecting circuit 6 is output through the output terminal 9.
In the above-described embodlment, the random error correction circuit 7 is provided with the circuit performing operation with modulo 2n-l, but there may be provided a random error correcting clrcuit using a conventional linear period shift register circuit. Furthermore, the code length ., .
is not definitely limited, but it is a matter of course that a similar effect can also be brought forth with a shortened code.
As described above, according to the present inven-tion, there can effectively be provided a higher reliable circuit for decoding a BCH code in order to correct a com-plex error by the provision of the output selecting circuit incorporating the criterion of selecting the outputs of the random error and burst error correcting circuits.
It is further understood by those skilled in the art that the foregoing description is a preferred embodiment of disclosed device and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.
and D.J. COSTELL0, Jr., pp. 280 - 282, published from Prentice-Hall, Inc., 1983.- In the figure, numeral 1 is an input terminal for inputting a received coded message, 39 is a burst-error-correcting unit for correcting a burst error by burst trapping, 40 is a random-error-correcting unit for correcting a random error, 6 is an output selecting circuit for selecting either the output from the burst-error-correcting unit 39 or the output from the random-error-correcting unit 40 and 9 is an output terminal for outputting an decoded result.
The operation of the above-mentioned prior art will now be described. A received message which has been decoded at a transmltter site before transmitting and includes errors added in the communication path is input from the input terminal 1 into both of the burst-error-correcting unit 39 and the random-error-correcting unit 40. The message is decoded by the respective correcting units, and either the decoded output from the burst-error-correcting unit 39 or the decoded output from the random-error-correcting unit 40 is selected by the output selecting circuit 6 in response to the condition of the communication path, and thereby the selected output is delivered from the output terminal 9 as an output of the complex error correct-ing circuit.
Since conventional complex error correcting circuitsare generally arranged as described above, it is necessary to control the output selecting circuit 6 in response to the condition of the communication path with respect to the con-crete error correcting code, but there is shown no definitesuggestion as to how the condition of the communication path can be concretely grasped and there is also shown no crite-rion to appropriately judge such a condition, therefore it is difficult to accurately control the selecting circuit 6.
There is a further problem that, because of the burst error correcting unit and the random error correcting unit being independently arranged from each other, it is necessary that the respective units independently include syndrome gener-ating circuits for extracting the error condition.
Summary of the Invention:
It is an object of the present invention to solvesuch problems as described above and to obtain an apparatus for decoding a BCH code signal and for correcting a complex - ~3~ 201 1 103 error combined in the BCH code signal whlch is capable of grasping the condition of the communication path, concretely providing a criterion for ~udging the condition of the communication path and commonly using a syndrome generating s circuit for a burst error correcting unit and a random error correcting unit.
This ob~ect is achieved by an apparatus for decoding a BCH code used for correcting a complex error which is capable of grasping the condition of a communication path by using the decoded result of a burst error correcting unit with a burst trapping functlon as well as the decoded result of the random error correcting unit having a circuit for deciding the result of an operation with a circuit for making an operation of integers of modulo 2n-1, thereby concretely providing a criterion for ~udging the condition of the communication path to control an output selecting circuit and there being further provided a means for converting a syndrome. thereby the common use of a syndrome generating circuit can be attained.
Accordingly, one aspect of the present invention relates to an apparatus for decoding a received BCH code signal on a communication path for correcting complex error comprising:
a syndrome generating circuit for generating two syndromes for correcting a random error of said BcH code signal;
-3a- 201 1 1 03 a first unit for correcting a random error of said BCH
code signal by using decoding means, said first unit being connected to said syndrome generating circuit to receive and use the two syndromes in correcting the random error;
a syndrome converting circuit, connected to said syndrome generating circuit, for converting said two syndromes into a single converted syndrome;
a second unit for correcting a burst error of said BCH
code signal by using decoding means, said second unit being connected to said syndrome generating circuit to receive and use the converted syndrome in correcting the burst error; and a third unit connected to said first and second units for deciding which output signal of said first or second unit is to be selectively output in response to the condition of the 5 communication path, said third unit including means for grasping the condition of the communication path, said means connected to the first and second units to receive decoded output signals from said first and second units wherein the output signals are used to grasp 0 the condition of the communication path, and means for judging the condition of the communication path as obtained by the means for grasping to determine which output signal of said first and second units is to be selectively output.
In a further aspect, the present invention relates to an apparatus for decoding a received BCH code signal for correcting a combined complex error, the apparatus comprising:
_ -3b-a first unit for correcting a random error of said BCH
code signal by using decoding means to produce a first decoded output signal and a first decoding condition signal;
a second unit for correcting a burst error of said BCH
code signal by using decoding means to produce a second decoded output signal and a second decoding condition signal, wherein a decoding condition signal relates to an indication of correctable or uncorrectable error detection by the respective unit; and a third unit connected to said first and second units for selecting one of the decoded output signals based on a combination of the first and second decoding condition signals and the first and second decoded output signals, said third unit including means for receiving the decoded output signals from said first and second units, means for determining which output signal of said first and second units is to be selectively output, means for determining whether at least one of the first and second decoded output signals is a correctable error signal, and means for providing an uncorrectable error output signal in response to a determination that neither the first nor second decoded output signal is a correctable error signal.
In a still further aspect, the present invention relates to an apparatus for decoding a received BCH code signal for correcting a combined complex error, the apparatus ,-- . .
-3c-comprising:
a random error decoder for receiving the BCH code signal and for providing a first decoded output signal, and a first decoding condition signal;
a burst error decoder for receiving the BCH code signal and for providing a second decoded output signal, and a second decoding condition signal, the first and 10 second decoding condition signal being indications of an error correction or an error detection; and a selector including means for receiving the first and second decoded output signals and the first and second decoding condition 5 signals from the decoders, and means for selecting one of the first and second decoded output signals based on the received signals.
In a further aspect, the present invention relates to an apparatus for decoding a received BCH code signal for 20 correcting a combined comp-lex error, the apparatus comprising:
a random error decoder for receiving the BCH code signal and for providing a first decoded output signal;
a burst error decoder for receiving the BCH code signal and for providing a second decoded output signal, and an 25 uncorrectable error signal for indicating whether there is an uncorrectable error; and _ -3d- 20 1 1 1 03 a selector for receiving the first and second decoded output signals and the uncorrectable error signal and for selecting and outputting one of the first and second decoded output signals based on the received signals.
In a still further aspect, the present invention relates to a method for providing a decoded output signal from an input signal, the method including the steps of:
providing a first error corrector which receives the input signal and provides a first decoded output signal and a first decoding condition signal;
providing a second error corrector which receives the input signal and provides a second decoded output signal and a second decoding condition signal, wherein the first and second error correctors correct errors in a different manner;
receiving the first and second decoded output signals and the first and second decoding condition signals; and selecting one of the first and second decoded output signals in response to the received signals.
Brief Description of the Dra~ings:
Flg. 1 illustrates a block diagram showing a conven-tional apparatus for decoding a BCH code with a correctlon function oi a complex error;
Fig. 2 is a block diagram showing an apparatus for decoding a BCH code with a correction function of a complex error according to thls invention;
Fig. 3 is a block diagram showing details of the random error correcting circuit shown in Fig. 2;
20~ 1 ~ 0~
Flg. 4 is a detailed dlagram of the burst error correcting clrcuit shown ln Fig. 2;
Fig. 5 shows a detailed diagram of the output select-ing circuit illustrated ln Fig. 2; and Fig. 6 is a table showing the criterion for control-ling the output selecting switch incorporated in the output selection control circuit shown in Fig. 5.
Detailed Description of the Preferred Embodiments:
An embodlment of the present lnventlon wlll now be described. Referring now to Flg. 2, there ls shown ln block dlagram form a error correcting unlt. In the drawing, numeral 1 denotes an input terminal for inputting a coded message received, 2 a syndrome generating circuit for gener-ating two n-bit syndromes for correcting a random error, 3 a lS delay circuit for holding the received message during the period of generating the syndromes and correcting an error, 4 a syndrome converting circuit for performing a conversion from the two n-bit syndromes generated in the syndrome generating circuit 2 to a 2n-bit syndrome for a burst trapping circuit for correcting a burst error, 5 a burst error correcting circuit for calculating the posi-tion in which a burst error is generated, and the pattern of the burst error, 6 an output selectlng circuit incorporating a criterion for grasping and ~udging the condition of a communlcatlon path by uslng the decoded results of the burst error correcting circult 5 and a random error correctlng circuit mentioned next, 7 a random error correcting circuit for recelving, as an lnput, the syndrome which is vector C
-expressed by the polynomial basis in a finite field and obtained with the syndrome generating circuit 2, converting the syndrome vector-expressed syndrome to an exponential expression of a primitive element of the finite field, obtaining an error position polynomial by normalizing the converted exponential repression with an integer operation of modulo 2n-1, obtaining the radical of the normalized error position polynomial by looking up a table of the normalized error position pre-calculated the constant terms of the normalized error position polynomial, calculating the true error position from the normalized error position, and correcting the random error, 8 a data ROM for storing data for converting the syndrome vector-expressed by the poly-nomial basis in the finite field obtained by the syndrome generating circuit 2 into the exponential expression of the primitive element of the finite field and data of the norma-lized error position which is the radical of the normalized error position polynomial, 9 an output terminal for output-ting the decoded results, 10 a terminal for outputting a signal when a uncorrectable error showing the final decoded condition is detected, and ll-a and ll-b exclusive OR
circuits for adding error correction pulses output from the burst error and random error correcting circuits 5 and 7 to the received message.
Fig. 3 shows the details of the random error correct-ing circuit 7 shown in Fig. 2, and in this figure, numeral 12 is an input terminal for inputting the syndrome vector-expressed with the polynomial basis in the finite field _ -6- ~ 01 1 103 obtained by the syndrome ~enerating circuit 2 shown in Fig. 2, 13 a register for holding the input syndrome, 14 an adding circuit with modulo 2 -1, 15 .~
a complementary number circuit with modulo 2 -1, 16 a register for temporarily holding data, 17 a register having a function for checking the results of calculation by the adding circuit 14 with modulo 2n-1 and the complementary number circuit 15 with modulo 2n-1, 18 a counter circuit for calculating the true error position, 19 an OR circuit for mixlng the correction pulses output from the counter circuits 18 and 18, 20 an address control circuit for outputting an address to the data ROM 8 which stores the data for converting the syndrome vector-expressed with the polynomial basis in the finite field to the expo-nential expression of the primitive element of the finitefield and the data of the normalized error position which is a radical of the normalized error position polynomial, 21 an address terminal for outputting and address to the data ROM
8, 22 a data input terminal to which data are inputted from the data ROM 8, 23 an output terminal for outputting the correction pulse, and 24 a terminal for outputting a un-correctable error detection signal when an error which can not be corrected at the random error correcting circuit 7.
Fig. 4 shows the details of the burst error correct-ing circuit 5 shown in Fig. 2 in which numeral 25 is an input terminal for inputting the output of the syndrome converting circuit 4 illustrated in Fig. 2, 26 a l-bit delay circuit, 27 a switch for controlling a feedback circuit B
consisting of the delay circuits 26 connected in loop through the switch, 28 a selecting switch for selecting either the output from the syndrome converting circuit 4 or the data from the feedback circuit, 29 a trapping (zero detection) circuit for detecting the fact that the upper (2n-b)-bits of the linear feedback shift register, or the feedback circuit having 2n-bits in length become zero, 30 a terminal outputting a uncorrectable burst error detection signal when an error which can not be corrected at the burst error correcting circuit 5 is detected, and 31 an error-pattern output terminal for serially outputting an error-pattern to be corrected when the burst error is corrected.
Fig. 5 is a detailed block diagram of the output selecting circuit 6 shown in Fig. 2 including the criterion for grasping and judging the condition of the communication path by using the decoded results of the burst error and random error correcting circuits 5 and 7 shown in Fig. 2.
In Fig. 5, numeral 32 denotes an input terminal for the data which has been corrected by using the output from the random error correcting circuit 7, 33 an input terminal for data which has been corrected by using the output from the burst error correcting circuit 5, 34 an exclusive OR circuit for comparing the data corrected by the random error correcting circuit 7 and the data corrected by the burst error correct-ing circuit 5, 35 an input terminal of the uncorrectableerror detection signal from the terminal 24 related to the random error correcting circuit 7, 36 an input terminal of the uncorrectable error detection signal from the terminal 31 related to the burst error correcting circuit 5, 37 an output selecting switch for selecting either the data corrected by the random error correcting circuit 7 or the data corrected by the burst error correcting circuit 5, s and 38 an output selection control circuit for generating a uncorrectable signal to the terminal 10 (shown in Figs. 2 and 4) depending on the uncorrectable error detection signals input from the random and burst error correcting circuits 7 and 5 to the input terminals 35 and 36, and the generating a control signal for controlling the output selecting switch 37 in accordance with the error detection signals and the output signal from the exclusive OR circuit 34 which compares the data input to the terminal 32, which has been corrected by the random error correcting circuit 7 and the data input to the terminal 33, which has been corrected by the burst error correcting circuit 5.
Fig. 6 is a table showing the criterion for control-ling the output selecting switch 37 incorporated in the selecting circuit 6 and the criterion for deciding the uncorrectable error signal to the terminal 10.
The operation will now be described. A message which has been coded at a transmitter side and includes errors added at the communication path is received at the input terminal 1. Two n-bit syndromes S1, S3 expressed by vectors of the polynomial basis in the finite field is generated by the syndrome generating circuit 2. The two n-bit syndromes S 1, S3 are then input to the random error correcting circuit 7 and the syndrome converting circuit 4. In the random ~` 201 1 1 03 g error correcting circuit 7, the input syndromes Sl, S3 are held in the register 13 and output as address of the data ROM 8 through the address control circuit 20 to the address output terminal 21. The syndromes Sl, S3 are converted by the data ROM 8 from the vector expression with the polynomial basis in the finite field to the exponential expression of primitive element of finite field, log Sl and log S3 . The converted syndromes log Sl and log S3, are stored into the register 16 by way of the data input terminal 22 and the register 17. Based on the exponentially expressed syndromes log Sl and log S3 stored in the register 16, the constant term (log S3 - log Sl) of the normalized error position polynomial is calculated using the adding circuit 14 and the complementary number circuit 15, and the constant term (log S3 - 3 x log S1) is then output as address of the data ROM 8 through the address control circuit 20 and the address output terminal 21. The constant term (log S3 - 3 x log S1) is then converted by the data ROM 8 to two radicals i =
log ~i and j = log ~j of the normalized error position poly-nomial. Herein, ~ is a primitive element of finite field and ~i and ~i are radicals of the normalized error position polynomial, i.e., are represented the normalized error position. The two radicals i = log ~i and j = log ~j of the error position polynomial normalized by the data ROM 8 are directed through the data input terminal 22 and the register 17 and added by the adding circuit 14 with log S
and stored in the counter circuit 18 for calculating o- 2~ 3 the true error position. At this time, the result of addition is checked by the register 17, and if it is in a uncorrectable condition, a uncorrectable error detection signal is output to the terminal 24. The true error position stored in the counter circuit 18 is counted down, and when the content of the counter circuit 18 becomes zero, an error correction pulse is given through the OR
circuit 19 to the exclusive OR circuit ll-a.
On the other hand, the two n-bit syndromes S1 and S3 input into the syndrome converting circuit 4 are converted to 2n-bit syndromes and thereafter input to the burst error correcting circuit 5. For example, for (511, 493) BCH codes having the generated polynomial of:
g(x) = Xl8 + X15 + X12 + X10 + x8 + X7 + x6 + X3 + 1 the conversion is performed in accordance with the following equations:
Slo = Sl7 + Sl4 + Sl3 + Sl1- 1 + S37 + S34 + S33 + S31 Sl8 + S15 + S14 + Sl2 + Sll + Slo + S38 + S35 + S34 + S31 + S3O
2 S16 + S15 + Sl3 + S12 + Sl 1 + Slo + S36 + S3s + S33 + S31 + S3O
S13 = S16 + S12 + S36 + S33 + S32 S14 = Sl7 + Sl3 + S37 + S34 33 S15 = S18 + S14 + Slo + S38 + S3s 34 3 S16 = Sl7 + Sl5 + Sl4 + S13 S37 + S36 + S3s + S34 + S33 7 Sl8 + Sl7 + Sl6 + Sl5 + S13 + Sl r 3 36 35 S33 + S31 8 Sl8 + Sl6 + Sl3 + Sl2 + Sl1 + S1O
S36 + S33 + S32 + S31 + S3O
Sls = S17 + S14 + S13 + S1 S37 + S34 + S33 + S32 + S
Sll o = Sl8 + S17 + S15 +
S38 + S37 + S3s + S32 + S
Sll 1 = Sl8 + Sl6 + S13 + Sl2 1 S38 + S36 + S33 + S32 + S3O
S112 = S1O + S3O
Sll3 = Sll + S31 Sll4 = Sl2 + S32 Sl 1 s = Sl7 + Sl4 + Sl 1 + S10 + S37 + S34 + S31 + S3O
Sll6 Sl8 Sl5 Sl2 S
+ S38 + S3s + S32 + S
S1l7 = Sl6 + Sl3 + Sl2 + S1O
+ S36 + S33 + S32 + S3O
In the burst error correcting circuit 5, the switch 27 for controlling the feedback is closed and the selecting switches 28 are turned to the sides "a" connected to the input terminals 25 so that the two n-bit syndromes converted by the syndrome converting circuit 4 are inputted to the delay circuit 26 of the linear feedback shift register circuit having 2n-bit in length. The selecting switch 28 is then turned to the linear feedback shift register circuit sides "b" and the burst error pattern is checked by the trapping (zero detection) circuit 29 while performing the shifting operation. If the burst error pattern is detected If an error pattern is detected at the random error correcting circuit 7 or the burst error correcting circuit 5, the received message is read out from the delay circuit 3 in which the received message has been held, the respective error patterns detected at the random and burst error correcting clrcuits 7 and 5 are separately combined to the received message by the exclusive OR circuits ll-a, ll-b, and thus the random and burst errors are corrected to provide thelr decoded messages. Thereafter, the decoded messages corrected by the random error and burst error correcting circuits 7 and 5 and the outputs from the un-correctable error detectlon terminals 24, 30 connected to the random error and burst error correcting circuits 7 and 5 are input to the output selecting circuit 6. In the output selecting circuit 6, the respective messages input from the random error and burst error correcting clrcuits 7 and 5 are compared by the e~cluslve OR circuit 34. The result of com-parlson by the excluslve OR circuit 34 and the uncorrectableerror detectlon slgnals from the terminals 24, 30 are lnput to the output selection control clrcult 38 whlch, ln turn, controls the output selecting switch 37 in accordance wlth , ,, ' f' 201 1 1~
-the criterion of output selectlon shown ln Flg. 6. Thus, if both of the uncorrectable error detection signals from the terminals 24, 30 show the correction and the output of the exclusive OR circuit 34 which compares the respective decoded messages shows the decoded messages being identical, then the output selecting switch 37 is turned to its ~a~-side to select the output of the random error correcting circuit 7 through the exclusive OR circuit ll-a, and if the uncorrectable error detection signal from the terminal 24 shows correction and the uncorrectable error detection signal from the terminal 30 shows detection of any un-correctable error, the output selecting switch 37 is turned to its "a~-side to select the same output as the above, and if the uncorrectable error detectlon slgnal from the terminal 30 shows correctlon and the uncorrectable error detectlon slgnal from the terminal 24 shows detection of any uncorrectable error, then the output selectlng swltch 37 is turned to its "b~-side to select the output of the burst error correcting circuit 5 through the exclusive OR circuit ll-b, and in other cases, the signal which represents the existence of uncorrectable error is output at the terminal lO. The final decoded message selected by the output selecting circuit 6 is output through the output terminal 9.
In the above-described embodlment, the random error correction circuit 7 is provided with the circuit performing operation with modulo 2n-l, but there may be provided a random error correcting clrcuit using a conventional linear period shift register circuit. Furthermore, the code length ., .
is not definitely limited, but it is a matter of course that a similar effect can also be brought forth with a shortened code.
As described above, according to the present inven-tion, there can effectively be provided a higher reliable circuit for decoding a BCH code in order to correct a com-plex error by the provision of the output selecting circuit incorporating the criterion of selecting the outputs of the random error and burst error correcting circuits.
It is further understood by those skilled in the art that the foregoing description is a preferred embodiment of disclosed device and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.
Claims (34)
1. An apparatus for decoding a received BCH code signal on a communication path for correcting complex error comprising:
a syndrome generating circuit for generating two syndromes for correcting a random error of said BCH code signal;
a first unit for correcting a random error of said BCH
code signal by using decoding means, said first unit being connected to said syndrome generating circuit to receive and use the two syndromes in correcting the random error;
a syndrome converting circuit, connected to said syndrome generating circuit, for converting said two syndromes into a single converted syndrome;
a second unit for correcting a burst error of said BCH
code signal by using decoding means, said second unit being connected to said syndrome generating circuit to receive and use the converted syndrome in correcting the burst error; and a third unit connected to said first and second units for deciding which output signal of said first or second unit is to be selectively output in response to the condition of the communication path, said third unit including means for grasping the condition of the communication path, said means connected to the first and second units to receive decoded output signals from said first and second units wherein the output signals are used to grasp the condition of the communication path, and means for judging the condition of the communication path as obtained by the means for grasping to determine which output signal of said first and second units is to be selectively output.
a syndrome generating circuit for generating two syndromes for correcting a random error of said BCH code signal;
a first unit for correcting a random error of said BCH
code signal by using decoding means, said first unit being connected to said syndrome generating circuit to receive and use the two syndromes in correcting the random error;
a syndrome converting circuit, connected to said syndrome generating circuit, for converting said two syndromes into a single converted syndrome;
a second unit for correcting a burst error of said BCH
code signal by using decoding means, said second unit being connected to said syndrome generating circuit to receive and use the converted syndrome in correcting the burst error; and a third unit connected to said first and second units for deciding which output signal of said first or second unit is to be selectively output in response to the condition of the communication path, said third unit including means for grasping the condition of the communication path, said means connected to the first and second units to receive decoded output signals from said first and second units wherein the output signals are used to grasp the condition of the communication path, and means for judging the condition of the communication path as obtained by the means for grasping to determine which output signal of said first and second units is to be selectively output.
2. An apparatus according to claim 1 wherein said first unit comprises:
random error correcting means for calculating a true random error position of said received BCH code signal in accordance with said syndromes and outputting a random error correction signal; and first combining means for combining said random error correction signal with said received BCH code signal, thereby a random error corrected BCH code signal is output.
random error correcting means for calculating a true random error position of said received BCH code signal in accordance with said syndromes and outputting a random error correction signal; and first combining means for combining said random error correction signal with said received BCH code signal, thereby a random error corrected BCH code signal is output.
3. An apparatus according to claim 2 wherein said random error correcting means comprises:
means for converting patterns of said syndromes generated by said syndrome generating circuit to an exponential expression with primitive elements;
means for normalizing said converted exponential expression with an integer operation of modulo 2n-1 so as to obtain an error position polynomial wherein n coresponds to the number of bits in each of the two syndromes;
means for looking up a table storing pre-calculated roots of said error position polynomial and for obtaining a normalized error position; and means for calculating said true random error position based on said obtained normalized error position to output said random error correction signal.
means for converting patterns of said syndromes generated by said syndrome generating circuit to an exponential expression with primitive elements;
means for normalizing said converted exponential expression with an integer operation of modulo 2n-1 so as to obtain an error position polynomial wherein n coresponds to the number of bits in each of the two syndromes;
means for looking up a table storing pre-calculated roots of said error position polynomial and for obtaining a normalized error position; and means for calculating said true random error position based on said obtained normalized error position to output said random error correction signal.
4. An apparatus according to claim 2 wherein said second unit comprises:
burst error correcting means for calculating a true burst error position of said received BCH code signal in accordance with the single converted syndrome, said single converted syndrome being a 2n-bit syndrome wherein n corresponds to the number of bits in each of the two syndromes, and outputting a burst error correction signal; and second combining means for combining said burst error correction signal to said received BCH code signal, thereby a burst error corrected BCH code signal is output.
burst error correcting means for calculating a true burst error position of said received BCH code signal in accordance with the single converted syndrome, said single converted syndrome being a 2n-bit syndrome wherein n corresponds to the number of bits in each of the two syndromes, and outputting a burst error correction signal; and second combining means for combining said burst error correction signal to said received BCH code signal, thereby a burst error corrected BCH code signal is output.
5. An apparatus according to claim 4 wherein said random error correcting means includes first detecting means for detecting an uncorrectable random error and said burst error correcting means includes second detecting means for detecting an uncorrectable burst error.
6. An apparatus according to claim 5 wherein said third unit comprises:
switching means for selectively outputting one of the outputs from said first and second combining means;
third detecting means for detecting whether or not said outputs from said first and second combining means are the same; and control means connected to said first and second detecting means of said first and second unit and said third detecting means, for outputting a switching control signal to said switching means.
switching means for selectively outputting one of the outputs from said first and second combining means;
third detecting means for detecting whether or not said outputs from said first and second combining means are the same; and control means connected to said first and second detecting means of said first and second unit and said third detecting means, for outputting a switching control signal to said switching means.
7. An apparatus according to claim 4 wherein said burst error correcting means comprises 2n-bit linear feedback shift register means which inputs said 2n-bit syndrome and trapping detecting means for detecting a burst error pattern of said registered 2n-bit syndrome by means of zero detection.
8. An apparatus according to claim 4 further comprising delay means for holding said received BCH code signal till said random and burst error correcting means output said random and burst error correction signal and thereafter outputting said received BCH code signal.
9. An apparatus for decoding a received BCH code signal for correcting a combined complex error, the apparatus comprising:
a first unit for correcting a random error of said BCH
code signal by using decoding means to produce a first decoded output signal and a first decoding condition signal;
a second unit for correcting a burst error of said BCH
code signal by using decoding means to produce a second decoded output signal and a second decoding condition signal, wherein a decoding condition signal relates to an indication of correctable or uncorrectable error detection by the respective unit; and a third unit connected to said first and second units for selecting one of the decoded output signals based on a combination of the first and second decoding condition signals and the first and second decoded output signals, said third unit including means for receiving the decoded output signals from said first and second units, means for determining which output signal of said first and second units is to be selectively output, means for determining whether at least one of the first and second decoded output signals is a correctable error signal, and means for providing an uncorrectable error output signal in response to a determination that neither the first nor second decoded output signal is a correctable error signal.
a first unit for correcting a random error of said BCH
code signal by using decoding means to produce a first decoded output signal and a first decoding condition signal;
a second unit for correcting a burst error of said BCH
code signal by using decoding means to produce a second decoded output signal and a second decoding condition signal, wherein a decoding condition signal relates to an indication of correctable or uncorrectable error detection by the respective unit; and a third unit connected to said first and second units for selecting one of the decoded output signals based on a combination of the first and second decoding condition signals and the first and second decoded output signals, said third unit including means for receiving the decoded output signals from said first and second units, means for determining which output signal of said first and second units is to be selectively output, means for determining whether at least one of the first and second decoded output signals is a correctable error signal, and means for providing an uncorrectable error output signal in response to a determination that neither the first nor second decoded output signal is a correctable error signal.
10. An apparatus according to claim 9 wherein said first unit comprises:
means for generating two n-bit syndromes in accordance with said received BCH code signal;
random error correcting means for calculating a random error position of said received BCH code signal in accordance with said syndromes and for outputting a random error correction signal based on the random error position;
and first combining means for combining said random error correction signal with said received BCH code signal and for outputting a random error corrected BCH code signal.
means for generating two n-bit syndromes in accordance with said received BCH code signal;
random error correcting means for calculating a random error position of said received BCH code signal in accordance with said syndromes and for outputting a random error correction signal based on the random error position;
and first combining means for combining said random error correction signal with said received BCH code signal and for outputting a random error corrected BCH code signal.
11. An apparatus according to claim 10 wherein said random error correction means comprises:
means for converting patterns of said syndromes generated by said means for generating to an exponential expression with primitive elements;
means for normalizing said converted exponential expression with an integer operation of modulo 2n-1 so as to obtain an error position polynomial;
means for looking up a table storing pre-calculated roots of said error position polynomial and for obtaining a normalized error position; and means for calculating said random error position based on said obtained normalized error position to output said random error correction signal.
means for converting patterns of said syndromes generated by said means for generating to an exponential expression with primitive elements;
means for normalizing said converted exponential expression with an integer operation of modulo 2n-1 so as to obtain an error position polynomial;
means for looking up a table storing pre-calculated roots of said error position polynomial and for obtaining a normalized error position; and means for calculating said random error position based on said obtained normalized error position to output said random error correction signal.
12. An apparatus according to claim 10 wherein said second unit comprises:
means for converting said two n-bit syndromes generated by said generating means of said first means to 2n-bit syndrome;
burst error correcting means for calculating a burst error position of said received BCH code signal in accordance with said 2n-bit syndrome and outputting a burst error correction signal; and second combining means for combining said burst error correction signal and said received BCH code signal, and for outputting a burst error corrected BCH code signal.
means for converting said two n-bit syndromes generated by said generating means of said first means to 2n-bit syndrome;
burst error correcting means for calculating a burst error position of said received BCH code signal in accordance with said 2n-bit syndrome and outputting a burst error correction signal; and second combining means for combining said burst error correction signal and said received BCH code signal, and for outputting a burst error corrected BCH code signal.
13. An apparatus according to claim 12 wherein the first and second decoding condition signals are uncorrectable error signals, wherein said random error correcting means includes first detecting means for detecting an uncorrectable random error and for providing an uncorrectable random error signal, and said burst error correcting means includes second detecting means for detecting an uncorrectable burst error and for providing an uncorrectable burst error signal.
14. An apparatus according to claim 13 wherein said third unit comprises:
switching means for selectively outputting one of the outputs from said first and second combining means;
third detecting means for detecting whether or not said outputs from said first and second combining means are the same and for providing a signal indicating whether said outputs are the same; and control means, connected to said first and second detecting means of said first and second unit, respectively, and to said third detecting means, for outputting a switching control signal to said switching means in response to the signals from the first, second, and third detecting means.
switching means for selectively outputting one of the outputs from said first and second combining means;
third detecting means for detecting whether or not said outputs from said first and second combining means are the same and for providing a signal indicating whether said outputs are the same; and control means, connected to said first and second detecting means of said first and second unit, respectively, and to said third detecting means, for outputting a switching control signal to said switching means in response to the signals from the first, second, and third detecting means.
15. An apparatus according to claim 12 wherein said burst error correcting means comprises:
2n-bit linear feedback shift register means having a plurality of stages which receives said 2n-bit syndrome, and trapping detecting means coupled between at least some of the stages of the shift register means for detecting a burst error pattern of said registered 2n-bit syndrome by means of zero detection.
2n-bit linear feedback shift register means having a plurality of stages which receives said 2n-bit syndrome, and trapping detecting means coupled between at least some of the stages of the shift register means for detecting a burst error pattern of said registered 2n-bit syndrome by means of zero detection.
16. An apparatus according to claim 12 further comprising delay means for holding said received BCH code signal until said random and burst error correcting means output said random and burst error correction signals, and for thereafter outputting said received BCH code signal to said first and second combining means.
17. An apparatus according to claim 9 wherein said first unit comprises:
means for generating syndromes, and means for detecting uncorrectable errors in response to a combination of syndromes from the generating means and for providing the first decoding condition signal indicating whether there are uncorrectable errors; and wherein said second unit comprises means for detecting that no correctable burst error exists within a length of a received code and for providing the second decoding condition signal indicating whether a correctable burst error exists within the length of code.
means for generating syndromes, and means for detecting uncorrectable errors in response to a combination of syndromes from the generating means and for providing the first decoding condition signal indicating whether there are uncorrectable errors; and wherein said second unit comprises means for detecting that no correctable burst error exists within a length of a received code and for providing the second decoding condition signal indicating whether a correctable burst error exists within the length of code.
18. An apparatus according to claim 9 wherein the first and second decoding condition signals and the first and second decoding output signals are provided to the third unit to select either one of the first and second output signals based on a combination of the first and second decoding condition signals and the first and second decoding output signals, wherein the first and second decoding condition signals indicate whether there is a correctable random error or burst error, respectively.
19. An apparatus according to claim 18 wherein the third unit selects:
the first output signal in response to an output signal from the first unit and second decoding condition signal indicating that there is an uncorrectable error;
the second output signal in response to an output signal from the second unit and a first decoding condition signal indicating that there is an uncorrectable error;
neither output signal in response to a signal from the first and second decoding condition signals indicating that there is an uncorrectable error in each unit.
the first output signal in response to an output signal from the first unit and second decoding condition signal indicating that there is an uncorrectable error;
the second output signal in response to an output signal from the second unit and a first decoding condition signal indicating that there is an uncorrectable error;
neither output signal in response to a signal from the first and second decoding condition signals indicating that there is an uncorrectable error in each unit.
20. An apparatus for decoding a received BCH code signal for correcting a combined complex error, the apparatus comprising:
a random error decoder for receiving the BCH code signal and for providing a first decoded output signal, and a first decoding condition signal;
a burst error decoder for receiving the BCH code signal and for providing a second decoded output signal, and a second decoding condition signal, the first and second decoding condition signal being indications of an error correction or an error detection; and a selector including means for receiving the first and second decoded output signals and the first and second decoding condition signals from the decoders, and means for selecting one of the first and second decoded output signals based on the first and second decoding condition signals, wherein the selecting means includes:
means for comparing the first and second decoded output signals and for providing a combined decoded signal, switching means which receives the first and second decoded output signals and provides as an output one of the first and second decoded output signals, and a control circuit for receiving the combined decoded signal, the first decoding condition signal, and the second decoding condition signal, and for actuating the switching means.
a random error decoder for receiving the BCH code signal and for providing a first decoded output signal, and a first decoding condition signal;
a burst error decoder for receiving the BCH code signal and for providing a second decoded output signal, and a second decoding condition signal, the first and second decoding condition signal being indications of an error correction or an error detection; and a selector including means for receiving the first and second decoded output signals and the first and second decoding condition signals from the decoders, and means for selecting one of the first and second decoded output signals based on the first and second decoding condition signals, wherein the selecting means includes:
means for comparing the first and second decoded output signals and for providing a combined decoded signal, switching means which receives the first and second decoded output signals and provides as an output one of the first and second decoded output signals, and a control circuit for receiving the combined decoded signal, the first decoding condition signal, and the second decoding condition signal, and for actuating the switching means.
21. The apparatus of claim 20 wherein the first and second decoded condition signals are signals which indicate the presence of an uncorrectable random error or burst error, respectively.
22. The apparatus of claim 21 wherein the means for selecting selects the first decoded signal in response to a first decoding signal and a second decoding condition signal indicating an uncorrectable burst error;
the second decoded signal in response to a second decoding signal and a first decoding condition signal indicating an uncorrectable random error; and neither decoded signal in response to first and second decoding condition signals indicating uncorrectable random and burst errors.
the second decoded signal in response to a second decoding signal and a first decoding condition signal indicating an uncorrectable random error; and neither decoded signal in response to first and second decoding condition signals indicating uncorrectable random and burst errors.
23. The apparatus of claim 20 wherein the random error decoder comprises:
means for providing a correction pulse;
means for delaying the received BCH code signal; and means for combining the correction pulse and the delayed BCH signal to form the first decoded output signal.
means for providing a correction pulse;
means for delaying the received BCH code signal; and means for combining the correction pulse and the delayed BCH signal to form the first decoded output signal.
24. The apparatus of claim 23 wherein the burst error decoder comprises:
means for providing an error pattern;
means for delaying the received BCH code signal; and means for combining the error pattern and the delayed BCH
signal to form the second decoded output signal.
means for providing an error pattern;
means for delaying the received BCH code signal; and means for combining the error pattern and the delayed BCH
signal to form the second decoded output signal.
25. The apparatus of claim 24 wherein the first and second decoded condition signals are signals which indicate the presence of an uncorrectable random error or burst error, respectively.
26. The apparatus of claim 20 wherein the combined decoded signal indicates whether the first and second decoded signals are identical to each other; and wherein the control circuit actuates the switching means in response to the combined decoded signal, the first decoding condition signal, and the second decoding condition signal.
27. The apparatus of claim 26 wherein the control circuit determines whether there is an uncorrectable error in response to the first and second decoding condition signals indicating an uncorrectable error;
switches the switching means to the first decoded output in response to a second decoding condition signal indicating an uncorrectable error; and switches the switching means to the second decoded output in response to a first decoding condition signal indicating an uncorrectable error.
switches the switching means to the first decoded output in response to a second decoding condition signal indicating an uncorrectable error; and switches the switching means to the second decoded output in response to a first decoding condition signal indicating an uncorrectable error.
28. The apparatus of claim 26 wherein the control circuit has means for providing an output signal indicating an uncorrectable error when the first and second decoding condition signal each indicate that there is no uncorrectable signal, and when the combined decoded signal indicates that the first and second decoded signals are not identical.
29. The apparatus of claim 26 wherein the means for comparing includes an Exclusive-OR logic element.
30. A method for providing a decoded output signal from an input signal, the method including the steps of:
providing a first error corrector which receives the input signal and provides a first decoded output signal and a first decoding condition signal;
providing a second error corrector which receives the input signal and provides a second decoded output signal and a second decoding condition signal, wherein the first and second error correctors correct errors in a different manner, and, wherein a decoding condition signal relates to an indication of correctable or uncorrectable error detection by the respective error correctors;
receiving the first and second decoded output signals and the first and second decoding condition signals; and selecting one of the first and second decoded output signals in response to the first and second decoding condition signals.
providing a first error corrector which receives the input signal and provides a first decoded output signal and a first decoding condition signal;
providing a second error corrector which receives the input signal and provides a second decoded output signal and a second decoding condition signal, wherein the first and second error correctors correct errors in a different manner, and, wherein a decoding condition signal relates to an indication of correctable or uncorrectable error detection by the respective error correctors;
receiving the first and second decoded output signals and the first and second decoding condition signals; and selecting one of the first and second decoded output signals in response to the first and second decoding condition signals.
31. The method of claim 30 wherein the first error corrector includes a random error corrector, and the second error corrector includes a burst error corrector.
32. The method of claim 30 wherein the receiving step includes the step of:
comparing the first and second decoded output signals to determine whether the first and second decoded output signals are identical.
comparing the first and second decoded output signals to determine whether the first and second decoded output signals are identical.
33. The method of claim 32 wherein, in response to a determination that the first and second decoded output signals are identical, the selecting step includes:
selecting one of the first or second decoded output signal if the first and second decoding condition signals indicate that both of the first and second error correctors have correctable errors; and selecting neither of the first or second decoded output signal and providing an uncorrectable error output signal if the first and second decoding condition signals indicate that both of the first and second error correctors have uncorrectable errors.
selecting one of the first or second decoded output signal if the first and second decoding condition signals indicate that both of the first and second error correctors have correctable errors; and selecting neither of the first or second decoded output signal and providing an uncorrectable error output signal if the first and second decoding condition signals indicate that both of the first and second error correctors have uncorrectable errors.
34. The method of claim 30 wherein the selecting step includes:
selecting the first decoded output signal if the first decoding condition signal indicates a correctable output signal and the second decoding condition signal indicates an uncorrectable output signal; and selecting the second decoded output signal if the second decoding condition signal indicates a correctable output signal and the first decoding condition signal indicates an uncorrectable output signal.
selecting the first decoded output signal if the first decoding condition signal indicates a correctable output signal and the second decoding condition signal indicates an uncorrectable output signal; and selecting the second decoded output signal if the second decoding condition signal indicates a correctable output signal and the first decoding condition signal indicates an uncorrectable output signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP121909/1989 | 1989-05-15 | ||
| JP1121909A JPH02301226A (en) | 1989-05-15 | 1989-05-15 | Composite error correction bch decoding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2011103A1 CA2011103A1 (en) | 1990-11-15 |
| CA2011103C true CA2011103C (en) | 1996-01-02 |
Family
ID=14822911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002011103A Expired - Fee Related CA2011103C (en) | 1989-05-15 | 1990-02-26 | Apparatus for decoding bose-chanhuri-hocqueghem code for correcting complex errors |
Country Status (11)
| Country | Link |
|---|---|
| JP (1) | JPH02301226A (en) |
| KR (1) | KR940002112B1 (en) |
| CA (1) | CA2011103C (en) |
| CH (1) | CH680031A5 (en) |
| DE (1) | DE4005533C2 (en) |
| FR (1) | FR2646976B1 (en) |
| GB (1) | GB2232043B (en) |
| IT (1) | IT1237726B (en) |
| NL (1) | NL191348C (en) |
| NO (1) | NO305879B1 (en) |
| SE (1) | SE512145C2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03235528A (en) * | 1990-02-13 | 1991-10-21 | Sharp Corp | Bch code decoding circuit |
| NL9101376A (en) * | 1990-08-16 | 1992-03-16 | Digital Equipment Corp | AN IMPROVED ERROR DETECTION CODING SYSTEM. |
| US5377208A (en) * | 1991-11-02 | 1994-12-27 | U.S. Philips Corporation | Transmission system with random error and burst error correction for a cyclically coded digital signal |
| JP2944489B2 (en) * | 1995-10-14 | 1999-09-06 | 日本電気株式会社 | Error correction method in wireless transmission system |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3544963A (en) * | 1968-12-27 | 1970-12-01 | Bell Telephone Labor Inc | Random and burst error-correcting arrangement |
| US4592054A (en) * | 1982-10-22 | 1986-05-27 | Mitsubishi Denki Kabushiki Kaisha | Decoder with code error correcting function |
| JPS5975732A (en) * | 1982-10-22 | 1984-04-28 | Mitsubishi Electric Corp | Decoder |
| GB2131253A (en) * | 1982-11-24 | 1984-06-13 | Motorola Ltd | Error-correcting decoder |
| GB2136248A (en) * | 1983-02-25 | 1984-09-12 | Philips Electronic Associated | Text error correction in digital data transmission systems |
| US4646303A (en) * | 1983-10-05 | 1987-02-24 | Nippon Gakki Seizo Kabushiki Kaisha | Data error detection and correction circuit |
| JPS61105931A (en) * | 1984-10-30 | 1986-05-24 | Mitsubishi Electric Corp | Decoder |
| JPS6276825A (en) * | 1985-09-30 | 1987-04-08 | Hitachi Ltd | Code error correcting method |
| JPS62268215A (en) * | 1986-05-16 | 1987-11-20 | Fuji Electric Co Ltd | Galois field arithmetic circuit |
| JPS6427322A (en) * | 1988-04-21 | 1989-01-30 | Sony Corp | Arithmetic circuit for galois field |
-
1989
- 1989-05-15 JP JP1121909A patent/JPH02301226A/en active Pending
- 1989-11-29 NO NO894757A patent/NO305879B1/en not_active IP Right Cessation
- 1989-12-11 SE SE8904169A patent/SE512145C2/en not_active IP Right Cessation
- 1989-12-18 NL NL8903084A patent/NL191348C/en not_active IP Right Cessation
- 1989-12-22 IT IT06815689A patent/IT1237726B/en active IP Right Grant
-
1990
- 1990-01-09 FR FR9000185A patent/FR2646976B1/en not_active Expired - Fee Related
- 1990-01-12 GB GB9000712A patent/GB2232043B/en not_active Expired - Fee Related
- 1990-01-25 CH CH239/90A patent/CH680031A5/de not_active IP Right Cessation
- 1990-02-19 DE DE4005533A patent/DE4005533C2/en not_active Expired - Fee Related
- 1990-02-26 CA CA002011103A patent/CA2011103C/en not_active Expired - Fee Related
- 1990-05-15 KR KR1019900006248A patent/KR940002112B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| GB9000712D0 (en) | 1990-03-14 |
| FR2646976B1 (en) | 1996-08-02 |
| DE4005533C2 (en) | 1998-01-22 |
| GB2232043B (en) | 1993-07-14 |
| IT8968156A0 (en) | 1989-12-22 |
| FR2646976A1 (en) | 1990-11-16 |
| NO894757L (en) | 1990-11-16 |
| JPH02301226A (en) | 1990-12-13 |
| KR940002112B1 (en) | 1994-03-17 |
| NO894757D0 (en) | 1989-11-29 |
| CH680031A5 (en) | 1992-05-29 |
| DE4005533A1 (en) | 1990-12-13 |
| NL8903084A (en) | 1990-12-03 |
| KR900019400A (en) | 1990-12-24 |
| NL191348C (en) | 1995-06-01 |
| GB2232043A (en) | 1990-11-28 |
| CA2011103A1 (en) | 1990-11-15 |
| IT1237726B (en) | 1993-06-15 |
| SE512145C2 (en) | 2000-01-31 |
| NO305879B1 (en) | 1999-08-09 |
| SE8904169L (en) | 1990-11-16 |
| SE8904169D0 (en) | 1989-12-11 |
| NL191348B (en) | 1995-01-02 |
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| EEER | Examination request | ||
| MKLA | Lapsed |