JPS62268215A - Galois field arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce a required arithmetic time by providing a gate circuit and a multiplier receiving an exponent being an output from the 1st conversion table and an optional integer and multiplying the both and switching an output from the 1st conversion table and an output from the multiplier selectively and supplying the result to an adder/subtractor. CONSTITUTION:An element alpha<i> of a Galois field GF(2<m>) is converted into an exponent (i) by a conversion table 1 and inputted to a multiplier 7 together with the integer (l). The multiplier 7 applies the operation of iXl. The operation is applied by using 2<m>-1 as the system. In opening a gate 5 and closing a gate 6, an adder/subtractor 3 adds the result of multiplication iXl by the multiplier 7 with the exponent (j) being an output of a conversion table 2 and the result is iXl+j. Further, the obtained result iXl+j is subject to anti-logarithm conversion by an inverse conversion table 4 and the result is outputted as alphaiXl+j. Thus, the operation of alpha<j>X(alpha<i>)<l> is executed. Thus, as the error correction capability is increased, the reduction rate of the required arithmetic time is increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a Galois field used to perform required operations in an error correction circuit for a digital signal transmitted in the form of an error correction code. This relates to arithmetic circuits.

[Conventional technology]

When transmitting or recording digital signals, data reflection occurs in the transmission system, and it is necessary to correct this. Data errors are correctly corrected with a very high probability by the correction circuit within the correction capability of the codes constituting the digital signal tube, and as a result, the error rate is improved.

There are various kinds of codes for error correction, but especially when a block code is used, a Reed-Saumon code, which is a type of BCH code, is often used.

When using this code, the necessary operations are performed by a Galois rest arithmetic circuit.

Figure @2 is a circuit diagram showing a conventionally known Galois rest arithmetic circuit as disclosed in Japanese Unexamined Patent Publication No. 57-155667.

In the same figure, 1 and 2 are conversion tables configured by ROM, etc., 3 is an adder/subtractor, and 4 is the same (RO
This is an inverse conversion table composed of M, etc.

The conversion table l is α as redundancy of Galois field GF(2)
This is a logarithmic conversion table that receives i as input and outputs its index i. Similarly, conversion table 2 is a Galois field GF(2)
This is an engraving conversion table which inputs α as the redundancy of , and outputs its index J'lr.

Note that the Galois field GF(2) itself is described in detail in the above-mentioned publication, so it will not be explained here.

The adder/subtractor 3 adds (
i+j=k) or subtraction (i-j=k), and the obtained result k is output to the inverse conversion table 4. In Table 4, the given finger Wik (=i±j) performs an antilog conversion to obtain the antilog number α, and outputs this.

In this way, if 3 is used as an adder, the output of inverse conversion table 4 will be α, and if 3 is used as a subtracter, the output of inverse conversion table 4 will be ・i−j. . However, addition/subtraction is performed as a (2-1)'e system.

From this result, when 3 is used as an adder, for j, a multiplication operation is performed to obtain .'><aj for α and α as redundancies in the Galois field GF(2), and 3 is subtracted.

In the case of using 1, K is that the division wave * to find α/α was similarly performed for 0□6jj.

Such Galois field arithmetic units are used in encoding circuits, syndrome generation circuits, division circuits, etc., and if the same Galois rest arithmetic circuit is used in a time-sharing manner, the capacity of the ROM required for the conversion table can be reduced. Can be done.

However, in the calculation for decoding using the Nyclid division method, it is necessary to perform the calculation of a When performing an operation using a circuit, it is necessary to repeat the same operation seven times,
especially! When the value becomes large, a problem arises in that the required calculation time increases.

[Problem that the invention seeks to solve]

Therefore, the present invention aims at α and j as elements of the Galois field.
The problem to be solved is to reduce the time required for the calculation of α×(α) between j j t α and j j t α .

Therefore, it is an object of the present invention to provide a Galois field arithmetic circuit that makes the above possible.

[Means and effects for solving the problems] The present invention has the following features:
The first conversion table receives an element .1 on the Galois field 0F(2) and outputs its index i, and the first conversion table receives an element α on the Galois field GF(2) and outputs its index i. index j
and a second conversion table that outputs the index if from the first conversion table and the index j from the second conversion table, and performs addition or subtraction between the two exponents. Addition output (i+j) or subtraction output (i-j)fi: Addition output (i+j) or subtraction output (i-j) is supplied from the adder/subtractor, and the multiplication of the two elements is performed. i+j
a third conversion table that outputs an i-j output (α) or a division output (α); and a Galois rest arithmetic circuit comprising an index i output from the first conversion table and an arbitrary integer! and a gate circuit that selectively switches between the output from the first conversion table and the output from the multiplier and supplies the output to the adder/subtractor. By using the output of the multiplier, the required calculation time is reduced.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In this figure, the same parts as in FIG. 2 are designated by the same reference numerals A-. In addition, 5 and 6 are gate circuits, and 7 is a multiplier. The multiplier 7 uses the index i output from the conversion tape /L-1 and an arbitrary integer! This is a circuit that inputs , multiplies the two, and outputs the result (lXi).

Next, the circuit operation will be explained. As is already clear, α as an element of the Galois field GF(2) is converted to an exponent 1 in the conversion table 1, which is an integer! It is also input to the multiplier 7. The multiplier 7 executes an operation (i×). This operation is performed using (2-1) as a system.

Now, if gate 5 is closed and gate 6 is opened, the circuit configuration shown in FIG. 1 becomes isometrically equivalent to the conventionally known Galois closed arithmetic circuit shown in FIG. When the gate 6 is opened and the gate 6 is closed, the adder/subtracter 3 performs addition between the multiplication result (i×l) in the multiplier 7 and the exponent j that is the output of the conversion table 2, and the result is ( iX
J+j). Furthermore, the obtained results (iXJ+j
) is converted into an antilog in the inverse conversion table 4, and ix
It is output as z+j.

As a result of the above, one line of calculation of ・j×(・i)t has been performed.

〔Effect of the invention〕

The decoding method using the Euclidean division method is efficient in performing multi-M corrections, and the decoding circuit is expandable. Now, assume that the final result of the adjoint polynomial can be expressed by the following equation.

In this equation, in order to check j such that U(,j)=0, if the code length is n, then according to the conventionally known Galois rest arithmetic circuit, (t(t+1)/2Xn) operations are required. However, according to the arithmetic circuit of the present invention, the required number of operations is (txn) times, which means that the operation time is reduced by (t+1)72 times.

From the above, it can be seen that the greater the error correction capability, the greater the reduction rate of the required calculation time according to the present invention.

[Brief explanation of drawings]

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventionally known Galois rest arithmetic circuit. Explanation of symbols 1.2...conversion table, 3...addition/
Subtractor, 4... Inverse conversion table, 5, 6...
...Gate circuit, 7... Multiplier agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzaki 1 Figure 9 α1 1+ 1 αL−ヱ α5−j Month 26 Pruning 2 Figure α lever

Claims (1)

[Claims] 1) A first conversion table that inputs α^i, which is an element on Galois field GF(2^m), and outputs its index i; a second conversion table that inputs the above element α^j and outputs its index j;
The above-mentioned exponent j is supplied from the conversion table of
an adder/subtractor that outputs an output (i+j) or a subtraction output (i-j), and an adder/subtracter that outputs an output (i+j) or a subtraction output (i-j) from the adder/subtractor, and a multiplication output (α
^i^+^j) or a third conversion table that outputs the division output (α^1^-^j); and an arbitrary integer l, and a multiplier that performs multiplication between the two; and a multiplier that selectively switches the output from the first conversion table and the output from the multiplier and supplies it to the adder/subtractor. A Galois field arithmetic circuit comprising a gate circuit.