KR0183279B1 - Decoder used for modified eculid algorithm - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Reed Solomon Decoder.

2. The technical problem to be solved by the invention

The modified Euclidean algorithm not only reduces the complexity of the circuit and the execution time of the calculation, but also provides a decoder that can be easily extended to other uses.

3. Summary of Solution to Invention

A polynomial generating means for calculating a modified syndrome polynomial value and a delete locator polynomial value, and an error / delete evaluator polynomial and an error / delete position calculated by calculating an error / delete evaluator polynomial and an error / delete locator polynomial. Corrected Euclidean algorithm execution means for outputting the child polynomial with the termination signal, time delay means, and error / delete value corrected in the error / delete position identified from the polynomial and the error / deletion locator polynomial. Means for evaluating and correcting polynomials for outputting the generated data.

4. Important uses of the invention

Decryptor.

Description

Decoder Using the Modified Euclidean Algorithm

The present invention relates to a decoder using a modified Euclid algorithm.

Reed-Solomon code decoding algorithms include the Paterson Gorenstein-Zierler algorithm, the Berlekamp Massey algorithm, the Euclid algorithm, and the modified Euclid algorithm.

Wolf helped recognize the superiority of this algorithm by demonstrating that the decoding technique of Paterson et al. Was closely related to the curve fitting algorithm described by Prony in 1795. However, it is less recommended than Euclid's algorithm for decoding Reed Solomon codes.

Algorithms such as Berlekamp are much more difficult to understand than methods such as Paterson, but inherently provide an efficient implementation. The complexity of the technique, such as Paterson, increases with the square of the number of errors to be corrected, thus providing an implementation for a binary BCH decoder that corrects up to six or seven errors. The complexity of the algorithm, such as Berlekamp, increases linearly to enable the construction of an efficient decoder that corrects dozens of errors.

The modified Euclid algorithm not only has the complexity of the algorithm such as Berlekamp, but also has the advantage of being easier to understand and apply.

Therefore, the present invention not only reduces the complexity of the circuit and the execution time of the calculation, but also can be easily extended to other uses and achieve parallelism. Thus, the modified Euclidean algorithm can be applied to real-time processing of broadband transmission such as multimedia. The purpose is to provide a used decoder.

1 is a block diagram of a decoder according to the present invention;

2 is a block diagram of a modified Euclidean algorithm performing unit according to the present invention;

3 is a block diagram of an error / erase evaluator polynomial calculator according to the present invention;

4 is a block diagram of an error / erase locator polynomial calculator according to the present invention;

5 is a configuration diagram of the operation cell according to the present invention,

6 is a block diagram of a terminal condition determiner according to the present invention,

7 is a block diagram of an error / erase evaluator and locator selector in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1: polynomial generator 2: modified Euclidean algorithm performer

3: time delay part 4: polynomial evaluation and correction part

Looking at the configuration of the present invention for achieving the above object, the present invention receives the received data and the deleted position information from the outside and calculates and outputs the modified syndrome polynomial value and the deleted locator polynomial value using the received data and the deleted position information. And a polynomial generating means for outputting a start signal, and a modified syndrome polynomial value, a delete locator polynomial value, and a start signal from the polynomial generating means. A correction Euclidean algorithm performing means for outputting the calculated error / deletion evaluator polynomial and the error / deletion locator polynomial together with the termination signal when the termination condition is satisfied and the data received by the polynomial generating means. Time delay means for delaying and outputting the self-calculation, and the modified eucli The error / deletion evaluator and locator polynomial value and the termination signal are input from the algorithm performing means, and the error / delete discriminated from the error / delete evaluator polynomial and the error / delete locator polynomial by receiving the delayed received data from the time delay means. And polynomial evaluation and correction means for correcting the corresponding error / erase value at the position and outputting the restored data.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a decoder according to the present invention. In the present invention, an example of a (n, k) Reed Solomon code capable of correcting any e errors and any E deletions will be described. do.

First, assuming that the minimum distance of this Reed Solomon code is d, a relationship of 2e + E d is established.

The polynomial generator 1 receives the received data and the deletion position information, and calculates the modified syndrome polynomial and the deletion position polynomial using the received data and the information about the deletion position. The calculated two polynomials are input to the modified Euclid algorithm performing section 2 together with the start signal.

The modified Euclid algorithm performing unit 2 uses the modified syndrome polynomial and the delete locator polynomial input from the polynomial generator 1 to generate the error / delete evaluator polynomial and the error / delete locator polynomial by the start signal. If the termination condition is satisfied, the calculated error / erase evaluator polynomial and the error / erase locator polynomial are output to the polynomial evaluation and correction unit 4 together with the termination signal.

The time delay unit 3 performs a function of delaying the received data for a predetermined time for which the error / erase evaluator polynomial and the error / erase locator polynomial are calculated and outputting the delayed data to the polynomial evaluation and correction unit 4.

The polynomial evaluation and correction unit 4 inputs the data input from the time delay unit 3 to the error / deletion position determined from the error / deletion evaluator polynomial inputted from the modified Euclidean algorithm performing unit 2 and the error / deletion locator polynomial. The received data is restored and output by correcting the corresponding error / erase value.

The modified Euclid algorithm performing unit 2 of the Reed-Solomon decoder performs the following operation repeatedly.

here,

When we say

to be.

Initial in the above operation Is Initial Is the product of the syndrome polynomial and the deletion locator polynomial. Is initialized to 0 Is initialized to the delete-position polynomial. The above operation Degree of It ends at a moment greater than.

Figure 2 shows the configuration of the modified Euclid (Euclid) algorithm performer in GF (2 ⁿ ) according to the present invention.

The modified Euclid algorithm performing unit 2 receives the syndrome polynomial and the start signal from the polynomial generator 1 and compares the order of the initial polynomial set by the start signal and the input syndrome polynomial according to the comparison result. A first operator 21 for calculating two error / deletion evaluator polynomials with different arithmetic coefficients, and a deletion locator polynomial and a start signal received from the polynomial generator 1, and from the first operator 21 A second operator 22 for calculating two error / deletion locator polynomials by receiving a cross discrimination signal and a degree of two polynomials and varying arithmetic coefficients of the polynomial according to the cross discrimination signal; and the first calculator 21. Receives the order of the cross discrimination signal and the two error / deletion evaluator polynomials, and receives the order of two error / deletion locator polynomials from the second operator 22. A termination condition determiner 23 for outputting a termination signal by comparing the order of the equation and the order of the error / erase locator polynomial, and the coefficient of the cross discrimination signal and the two error / erase evaluator polynomials from the first operator 21. Receives the coefficients of two error / deletion locator polynomials from the second operator 22 and selects the coefficients of one error / deletion evaluator polynomial and the coefficient of one error / delete locator polynomial And a selector 24 for outputting the evaluator polynomial and the error / delete locator polynomial.

The operation of the modified Euclidean algorithm performing unit 2 will be described below with reference to FIGS. 3 to 7.

3 shows a block diagram of a first calculator for calculating an error / erase evaluator polynomial, and FIG. 4 shows a block diagram of a second calculator for calculating an error / erase locator polynomial.

First, the first operator 21 for calculating an error / delete evaluator polynomial stores and outputs the operation value of the initial polynomial, and outputs the coefficient and order of the polynomial, and the operation value of the modified syndrome polynomial. Stores and outputs a second register 32 for outputting the order and coefficient of the polynomial, and receives a start signal from the polynomial generator 1, and receives the polynomial of the polynomial from the first and second registers 31 and 32. Compare the orders of the two polynomials received from the order input, if the degree of the initial polynomial input from the first register 31 is greater than the order of the polynomial input from the second register 32 in parallel the connection state of the switch And a cross discriminator 33 for outputting a cross discrimination signal for controlling the connection state of the switch to cross each other, and under the control of the cross discrimination signal output from the cross discriminator 33. A polynomial operation is performed on two values output from the first cross-bar switch 34 and the first cross-link switch 34 for switching the values output from the two registers 31 and 32. An operation cell 35 for outputting and an output value of the operation cell 35 to be switched by the cross discrimination signal of the cross discriminator 33 and output to the first and second registers 31 and 32. It consists of two cross-connected switches 36.

The second operator 22 that calculates the error / erase positioner polynomial receives one polynomial order from the first register 31 of the first operator, receives an operation value of the initial polynomial, stores it, and outputs it. And a single polynomial order from a first register 41 for outputting coefficients and orders of the polynomial, and a second register 32 of the first operator, and receiving an erase locator polynomial and calculating an erase locator polynomial. A second register 42 that stores and outputs a value, and outputs the order and coefficient of the polynomial, and the first and second registers 41 and 42 under the control of the cross discrimination signal output from the cross discriminator 33. A first cross-bar switch 43 for switching a value outputted from the first cross-link switch 43 and a calculation cell 44 for performing a polynomial operation on two values outputted from the first cross-connected switch 43 ), And the output of the operation cell 44 A second cross connect switch 45 is configured to switch a value by the cross discrimination signal of the cross discriminator 33 and output the same to the first and second registers 41 and 42.

Initial polynomial Corresponds to the A (X) register 31, which is the first register of the error / erase evaluator polynomial operator 21, and the syndrome polynomial Corresponds to B (X) register 32 which is the second register of the error / erase evaluator polynomial operator 21, Corresponds to the α (X) register 41, which is the first register of the error / erase locator polynomial operator 22, Corresponds to the β (X) register 42 which is the second register of the error / erase locator polynomial operator 22.

The error / erase evaluator polynomial operator 21 performs operations of Equations 1 and 2 until the termination condition is satisfied, and the error / erase positioner polynomial operator 22 performs equation 3 until the termination condition is satisfied. And the operation of equation (4).

The A (X) register 31 of the error / erase evaluator polynomial operator of FIG. The coefficient corresponding to the highest order term is initially selected by selecting the coefficient corresponding to the highest order term, and then inputted to the cross-connect switch 34, and the coefficient smaller by one order is input to the cross-connect switch 34 every clock until a constant term is input. . And, if it passes the constant term, input '0'.

The B (X) register 32 of FIG. 3 is initially polynomial A coefficient corresponding to the highest order term is initially selected and input to the cross-connect switch 34, and a coefficient one order smaller is input to the cross-connect switch 34 every clock until a constant term is input. . And, if it passes the constant term, input '0'. This process is repeated every clock until the coefficients input to the A (X) and B (X) registers 31 and 32 are all '0' difference.

The cross discriminator 33 compares the A-order inputted from the A (X) register 31 with the B-order inputted from the B (X) register 32. Are controlled in parallel, and if the A order is smaller than the B order, a cross discrimination signal for controlling the cross connection of the cross connection switches is output.

When the start signal indicating the start of the operation is applied, the cross discriminator 33 determines the value of σ by determining which polynomial of the polynomials of A (X) and B (X) is larger. If it is determined that the order of A (X) is greater, the cross discriminator 33 has the same effect as sigma = 1, and the two cross connect switches 34 and 36 are in a parallel connected state. This connection state is maintained until the coefficients of the two polynomials entered into the cross-connect switch are both entered through the constant term. If the order of B (X) is greater than the order of A (X), the cross discriminator 33 has the same effect as σ = 0, and the two cross-connect switches 34 and 36 remain cross-connected. .

In the equations (1) and (2), the order of R (X) is always equal to or greater than the order of Q (X), so if the cross judge 33 is σ = 1, then A (X) is considered R (X). , B (X) is considered to be Q (X), if cross discriminator 33 is σ = 0 then B (X) is considered to be R (X) and A (X) is considered to be Q (X). .

Register (41) of the error / erase locator polynomial operator of FIG. Is initialized to β (X), and the register 42 Initialize with. The coefficient term to be connected from the α (X) register 41 to the cross-connect switch is passed the coefficient at the same position as A (X), and in the case of the β (X) register 42 at the same position as B (X). Coefficients are selected and passed to the cross-connect switch. The cross connection switches 43 and 45 of the second calculator 22 are controlled by the cross discrimination signal, which is an output signal of the cross discriminator 33, similarly to the first calculator 21.

5 is a configuration diagram of an operation cell according to an embodiment of the present invention, in which an operation cell includes a first AND gate 51 configured to perform an AND operation on a start signal and an output of one side of the first cross-connect switch, and a start signal and the first signal. A second AND gate 52 for receiving and ORing the other output of the cross-connect switch, a first register 53 for temporarily storing and outputting the output of the first AND gate 51, and the second logic A second register 54 for temporarily storing and outputting the output of the product gate 52, a first multiplier 55 for multiplying the output value of the first register 53 with the other output value of the first cross-connect switch, A second multiplier 56 multiplying the output value of the second register 54 by the one-side output value of the first cross-connect switch, and the output value of the first multiplier 55 and the output value of the second multiplier 56. It consists of an adder 57.

If the coefficient of the highest order term of the A (X) and B (X) polynomials together with the start signal is input to the operation cell, when σ = 1, The register 54 is set to the highest order coefficient of the B (X) polynomial and is the first register. The register 53 is set to the highest order coefficient of the A (X) polynomial. Then, the operation is performed through the first and second multipliers 55 and 56 and the adder 57 as a result. Wow Is output.

And when sigma = 0, the second register Register 54 is set to the highest order coefficient of the A (X) polynomial and is the first register. The register 53 is set to the highest order coefficient of the B (X) polynomial. And as a result Wow Is output.

The result of the arithmetic cell is parallelly connected when σ = 1 by the cross discriminator 33, and crosses when A (X) and B (X are connected via the cross-connecting switch 36 which is cross-connected when σ = 0. ) Registers (31, 32). At this time, the coefficient term of the register to be stored becomes a register corresponding to the coefficient term outputted through the cross-connection switch 36.

6 is a configuration diagram of a termination condition determiner 23 according to the present invention, in which the termination condition determiner 23 is input from the first calculator 21 by a cross discrimination signal input from the first calculator 21. A first MUX 61 for selecting one of two error / deletion evaluator polynomials and a cross discrimination signal input from the first operator 21 and input from the second operator 22. A second mux 62 for selecting one of two error / deletion locator polynomials, and an output of the first mux 61 and an output of the second mux 62; The order of the two polynomials is compared and the comparator 63 outputs a termination signal when the degree of the polynomial selected in the second mux 62 is greater than the degree of the polynomial selected in the first mux 61.

Termination condition is Degree of Is greater than the order of. Therefore, using mux first Wow Select the order of under the control of the cross discrimination signal, and select the order of using the comparator 63 Degree of If the order is greater than, the termination signal indicating that the termination condition is satisfied is output.

7 is a block diagram of an error / erase evaluator and locator polynomial selector 24 according to the present invention, wherein the selector is controlled by a cross discrimination signal input from the first operator 21. Selects one of two coefficients of the error / deletion evaluator polynomial input from the first MUX 71 and outputs an error / deletion evaluator polynomial, and the cross discrimination signal input from the first operator 21. Under control, it consists of a second MUX 72 which selects one of the coefficients of the two error / erase locator polynomials input from the second operator 22 and outputs the error / erase locator polynomial.

The error / erase evaluator and locator polynomial selector 24 receives one coefficient out of two coefficients input using the first and second muxes 71 and 72 under the control of the cross discrimination signal when the termination condition is satisfied. Select each one Polynomials Determine the polynomial and output the error / delete evaluator polynomial and the error / delete locator polynomial, respectively.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

The present invention made as described above can reduce the complexity and execution time of the operation, can be easily extended to other uses, and can achieve parallelism, so that it can be applied to real-time processing of broadband transmission such as multimedia, as well as for synchronization. There is no need for an additional circuit, and there is an effect that operations can be performed with the same period even when the degree difference between the polynomials is more than one order.

Claims (9)

Polynomial generating means (1) for receiving the received data and the deleted position information from the outside, calculating and outputting the modified syndrome polynomial value and the deleted locator polynomial value using the received data and the deleted position information, and outputting a start signal; The modified syndrome polynomial value, the delete locator polynomial value, and the start signal are input from the polynomial generating means (1), and the error / delete evaluator polynomial and the error / delete locator polynomial are calculated based on the start signal. Correction Euclidean algorithm performing means (2) for outputting an error / erase evaluator polynomial and an error / erase locator polynomial with a termination signal; Time delay means (3) for delaying and outputting the data received by the polynomial generating means (1) while the error / erase evaluator and positioner are calculated; And The error / deletion evaluator and positioner polynomial values and the termination signal are received from the modified Euclidean algorithm performing means 2, and the error / deletion evaluator polynomial and error / delete position are received from the time delay means 3. And a polynomial evaluation and correction means (4) for outputting the restored data by correcting the error / deletion value at the error / deletion position determined from the polynomial. The method of claim 1, The modified Euclid (Eculid) algorithm performing means (2), The polynomial generating means 1 receives the syndrome polynomial and the start signal, compares the order of the initial polynomial set by the start signal and the input syndrome polynomial, and changes the operation coefficient values according to the comparison result to obtain an error / delete evaluator polynomial. First calculating means 21 for calculating; The polynomial generating means 1 receives a deletion positioner polynomial and a start signal, and receives a cross discrimination signal and a degree of two polynomials from the first calculating means 21. Second calculating means (22) for calculating the error / erase locator polynomial by differentiating the difference; Receive the order of the cross discrimination signal and the two error / erase evaluator polynomials from the first calculating means 21, and receive the order of two error / erase locator polynomials from the second calculating means 22; Termination condition determining means (23) for outputting a termination signal by comparing the degree of the delete evaluator polynomial with the order of the error / deletion locator polynomial; And Receives a cross discrimination signal and coefficients of two error / erase evaluator polynomials from the first calculating means 21 and receives two coefficients of error / erase locator polynomial from the second calculating means 22. And selecting means (24) for selecting the coefficients of the error / deletion evaluator polynomial and the coefficients of one error / deletion locator polynomial and outputting the error / deletion evaluator polynomial and the error / deletion locator polynomial. The method of claim 2, The first calculating means 21, First storage means (31) for storing and outputting an operation value of the initial polynomial and outputting coefficients and orders of the polynomial; Second storage means (32) for storing and outputting an operation value of the modified syndrome polynomial and outputting the order and coefficient of the polynomial; The first storage means 31 receives the start signal from the polynomial generating means 1, receives the orders of the polynomial from the first and second storage means 31 and 32, compares the orders of the two polynomials. If the order of the initial polynomial input in the () is greater than the order of the polynomial input from the second storage means 32 to control the connection state of the switch in parallel, otherwise the cross discrimination signal for controlling the connection state of the switch to cross A cross discrimination means 33 for outputting; First cross connection switching means (34) for switching the values output from the first and second storage means (31,32) under the control of the cross discrimination signal output from the cross discriminating means (33); Calculation means (35) for performing a polynomial operation on two values output from the first cross-connection switching means (34); And Second cross-connected switching means 36 for switching the output value of the calculation means 35 by the cross discrimination signal of the cross discriminating means 33 and outputting the first and second storage means 31, 32. Decoder comprising a. The method of claim 3, wherein The second calculating means 22, The first storage means 41 receives one polynomial order from the first storage means 31 of the first calculation means, receives and stores an operation value of the initial polynomial, and outputs coefficients and orders of the polynomial. ; Receiving one polynomial order from the second storage means 32 of the first computing means, receiving a delete locator polynomial, storing and outputting an operation value of the deleted locator polynomial, and outputting the order and coefficient of the polynomial Second storage means 42; First cross connection switching means (43) for switching the values output from the first and second storage means (41, 42) under the control of the cross discrimination signal output from the cross discriminating means (33); Calculation means (44) for performing a polynomial operation on two values output from the first cross-connection switching means (43); And Second cross-connected switching means 45 for switching the output value of the calculation means 44 by the cross discrimination signal of the cross discrimination means 33 and outputting the first and second storage means 41 and 42 to the first and second storage means 41 and 42. Decoder comprising a. The method according to claim 3 or 4, And said storage means comprises a register. The method according to claim 3 or 4, The calculating means, First logical multiplication means (51) for receiving the start signal and the output of one side of the first cross-connected switching means and logically multiply; Second logical multiplication means (52) for receiving the start signal and the other output of the first cross-connected switching means and logically multiply; A first register (53) for temporarily storing and outputting the output of the first logical multiplication means (51); A second register (54) for temporarily storing and outputting the output of the second logical product means (52); First multiplication means (55) for multiplying the output value of the first register (53) by the other output value of the first cross-connected switching means; Second multiplication means (56) for multiplying the output value of the second register (54) by the one-side output value of the first cross-connected switching means; And And an adding means (57) for adding the output value of the first multiplication means (55) and the output value of the second multiplication means (56). The method of claim 2, The termination condition determining means 23, First selecting means (61) for selecting one of the orders of the two error / erase evaluator polynomials input from the first calculating means (21) by the cross discrimination signal input from the first calculating means (21); Second selecting means (62) for selecting one of two orders of error / erase locator polynomial input from the second calculating means (22) by the cross discrimination signal input from the first calculating means (21); And The order of the polynomial selected by the second selecting means 62 is compared by receiving the output of the first selecting means 61 and the output of the second selecting means 62 and comparing the orders of the two polynomials. And a comparing means (63) for outputting a termination signal if it is larger than the order of the polynomial selected by the selecting means (61). The method of claim 2, The error / erase evaluator and locator polynomial selection means, Under the control of the cross discrimination signal input from the first calculating means 21, one of the coefficients of the two error / dropping evaluator polynomials input from the first calculating means 21 is selected to output an error / delete evaluator polynomial. First selecting means (71) for performing; And Under the control of the cross discrimination signal input from the first calculating means 21, one of the coefficients of the two error / deleting locator polynomials input from the second calculating means 22 is selected to select the error / delete locator polynomial. And a second selecting means (72) for outputting the same. The method according to claim 7 or 8, And the selecting means includes a mux.