CA1175581A - Data processing machine with improved cache memory management - Google Patents

Data processing machine with improved cache memory management

Info

Publication number
CA1175581A
CA1175581A CA000393741A CA393741A CA1175581A CA 1175581 A CA1175581 A CA 1175581A CA 000393741 A CA000393741 A CA 000393741A CA 393741 A CA393741 A CA 393741A CA 1175581 A CA1175581 A CA 1175581A
Authority
CA
Canada
Prior art keywords
cache
data
memory
central processor
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000393741A
Other languages
English (en)
French (fr)
Inventor
Horace H. Tsiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Wang Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories Inc filed Critical Wang Laboratories Inc
Application granted granted Critical
Publication of CA1175581A publication Critical patent/CA1175581A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855Overlapped cache accessing, e.g. pipeline
    • G06F12/0857Overlapped cache accessing, e.g. pipeline by multiple requestors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
CA000393741A 1981-01-07 1982-01-07 Data processing machine with improved cache memory management Expired CA1175581A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22315481A 1981-01-07 1981-01-07
US223,154 1988-07-22

Publications (1)

Publication Number Publication Date
CA1175581A true CA1175581A (en) 1984-10-02

Family

ID=22835271

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000393741A Expired CA1175581A (en) 1981-01-07 1982-01-07 Data processing machine with improved cache memory management

Country Status (10)

Country Link
JP (1) JPS57169990A (enrdf_load_stackoverflow)
BE (1) BE891723A (enrdf_load_stackoverflow)
CA (1) CA1175581A (enrdf_load_stackoverflow)
CH (1) CH656470A5 (enrdf_load_stackoverflow)
DE (1) DE3200042A1 (enrdf_load_stackoverflow)
FR (1) FR2497596B1 (enrdf_load_stackoverflow)
GB (1) GB2090681B (enrdf_load_stackoverflow)
IT (1) IT1154407B (enrdf_load_stackoverflow)
NL (1) NL8200043A (enrdf_load_stackoverflow)
SE (1) SE445270B (enrdf_load_stackoverflow)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617967A (ja) * 1984-06-15 1986-01-14 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション I/oコントロ−ラ
AU5634086A (en) * 1985-05-06 1986-11-13 Wang Laboratories, Inc. Information processing system with enhanced instruction execution and support control
US4814981A (en) * 1986-09-18 1989-03-21 Digital Equipment Corporation Cache invalidate protocol for digital data processing system
DE3920883A1 (de) * 1989-06-26 1991-01-03 Siemens Ag Verfahren und anordnung zur erhoehung der verarbeitungsgeschwindigkeit der zentraleinheit einer datenverarbeitungsanlage
JPH03189845A (ja) * 1989-12-13 1991-08-19 Internatl Business Mach Corp <Ibm> 階層メモリ・システムおよびキヤツシユ・メモリ・サブシステム
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ
JP5494643B2 (ja) 2009-02-20 2014-05-21 旭硝子株式会社 エレクトレットの製造方法及び静電誘導型変換素子

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
JPS51148334A (en) * 1975-06-16 1976-12-20 Hitachi Ltd Buffer memory control method
JPS5441291A (en) * 1977-09-09 1979-04-02 Sagami Chem Res Center Cluster fixed substance, production thereof and catalyst
US4169284A (en) * 1978-03-07 1979-09-25 International Business Machines Corporation Cache control for concurrent access
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations
GB2037039B (en) * 1978-12-11 1983-08-17 Honeywell Inf Systems Cache memory system

Also Published As

Publication number Publication date
NL8200043A (nl) 1982-08-02
GB2090681B (en) 1985-11-20
DE3200042C2 (enrdf_load_stackoverflow) 1991-03-07
GB2090681A (en) 1982-07-14
IT1154407B (it) 1987-01-21
SE445270B (sv) 1986-06-09
FR2497596A1 (fr) 1982-07-09
BE891723A (fr) 1982-04-30
JPH0353657B2 (enrdf_load_stackoverflow) 1991-08-15
IT8267010A0 (it) 1982-01-06
CH656470A5 (de) 1986-06-30
SE8107832L (sv) 1982-07-08
DE3200042A1 (de) 1982-08-19
FR2497596B1 (fr) 1989-03-03
JPS57169990A (en) 1982-10-19

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Legal Events

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