CA1159953A - V-mos device with self-aligned multiple electrodes - Google Patents

V-mos device with self-aligned multiple electrodes

Info

Publication number
CA1159953A
CA1159953A CA000377171A CA377171A CA1159953A CA 1159953 A CA1159953 A CA 1159953A CA 000377171 A CA000377171 A CA 000377171A CA 377171 A CA377171 A CA 377171A CA 1159953 A CA1159953 A CA 1159953A
Authority
CA
Canada
Prior art keywords
recess
substrate
layer
conductivity type
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000377171A
Other languages
English (en)
French (fr)
Inventor
Richard R. Garnache
Donald M Kenney
Nandor G. Thoma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1159953A publication Critical patent/CA1159953A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches

Landscapes

  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CA000377171A 1980-06-12 1981-05-08 V-mos device with self-aligned multiple electrodes Expired CA1159953A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US158,668 1980-06-12
US06/158,668 US4364074A (en) 1980-06-12 1980-06-12 V-MOS Device with self-aligned multiple electrodes

Publications (1)

Publication Number Publication Date
CA1159953A true CA1159953A (en) 1984-01-03

Family

ID=22569161

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000377171A Expired CA1159953A (en) 1980-06-12 1981-05-08 V-mos device with self-aligned multiple electrodes

Country Status (5)

Country Link
US (1) US4364074A (https=)
EP (1) EP0042084B1 (https=)
JP (1) JPS5713770A (https=)
CA (1) CA1159953A (https=)
DE (1) DE3165658D1 (https=)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3382688T2 (de) * 1982-02-10 1993-09-02 Hitachi Ltd Halbleiterspeicher und sein herstellungsverfahren.
US4567641A (en) * 1982-04-12 1986-02-04 General Electric Company Method of fabricating semiconductor devices having a diffused region of reduced length
US4571512A (en) * 1982-06-21 1986-02-18 Eaton Corporation Lateral bidirectional shielded notch FET
US4553151A (en) * 1982-09-23 1985-11-12 Eaton Corporation Bidirectional power FET with field shaping
US4542396A (en) * 1982-09-23 1985-09-17 Eaton Corporation Trapped charge bidirectional power FET
US4541001A (en) * 1982-09-23 1985-09-10 Eaton Corporation Bidirectional power FET with substrate-referenced shield
JPS60152058A (ja) * 1984-01-20 1985-08-10 Toshiba Corp 半導体記憶装置
USRE33261E (en) * 1984-07-03 1990-07-10 Texas Instruments, Incorporated Trench capacitor for high density dynamic RAM
US5208657A (en) * 1984-08-31 1993-05-04 Texas Instruments Incorporated DRAM Cell with trench capacitor and vertical channel in substrate
US4824793A (en) * 1984-09-27 1989-04-25 Texas Instruments Incorporated Method of making DRAM cell with trench capacitor
US5225697A (en) * 1984-09-27 1993-07-06 Texas Instruments, Incorporated dRAM cell and method
US4797373A (en) * 1984-10-31 1989-01-10 Texas Instruments Incorporated Method of making dRAM cell with trench capacitor
US4763177A (en) * 1985-02-19 1988-08-09 Texas Instruments Incorporated Read only memory with improved channel length isolation and method of forming
US5102817A (en) * 1985-03-21 1992-04-07 Texas Instruments Incorporated Vertical DRAM cell and method
US5017977A (en) * 1985-03-26 1991-05-21 Texas Instruments Incorporated Dual EPROM cells on trench walls with virtual ground buried bit lines
US5135879A (en) * 1985-03-26 1992-08-04 Texas Instruments Incorporated Method of fabricating a high density EPROM cell on a trench wall
US5164917A (en) * 1985-06-26 1992-11-17 Texas Instruments Incorporated Vertical one-transistor DRAM with enhanced capacitance and process for fabricating
US4751558A (en) * 1985-10-31 1988-06-14 International Business Machines Corporation High density memory with field shield
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
US4811067A (en) * 1986-05-02 1989-03-07 International Business Machines Corporation High density vertically structured memory
US4975384A (en) * 1986-06-02 1990-12-04 Texas Instruments Incorporated Erasable electrically programmable read only memory cell using trench edge tunnelling
US4829017A (en) * 1986-09-25 1989-05-09 Texas Instruments Incorporated Method for lubricating a high capacity dram cell
JPS63135737A (ja) * 1986-11-28 1988-06-08 Shimizu Constr Co Ltd クリ−ンル−ム
US4763180A (en) * 1986-12-22 1988-08-09 International Business Machines Corporation Method and structure for a high density VMOS dynamic ram array
US4874715A (en) * 1987-05-20 1989-10-17 Texas Instruments Incorporated Read only memory with improved channel length control and method of forming
US5109259A (en) * 1987-09-22 1992-04-28 Texas Instruments Incorporated Multiple DRAM cells in a trench
US4979004A (en) * 1988-01-29 1990-12-18 Texas Instruments Incorporated Floating gate memory cell and device
US5105245A (en) * 1988-06-28 1992-04-14 Texas Instruments Incorporated Trench capacitor DRAM cell with diffused bit lines adjacent to a trench
US5225363A (en) * 1988-06-28 1993-07-06 Texas Instruments Incorporated Trench capacitor DRAM cell and method of manufacture
KR920000708B1 (ko) * 1988-07-22 1992-01-20 현대전자산업 주식회사 포토레지스트 에치백 기술을 이용한 트렌치 캐패시터 형성방법
US5072266A (en) 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5057887A (en) * 1989-05-14 1991-10-15 Texas Instruments Incorporated High density dynamic ram cell
US5017506A (en) * 1989-07-25 1991-05-21 Texas Instruments Incorporated Method for fabricating a trench DRAM
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5053839A (en) * 1990-01-23 1991-10-01 Texas Instruments Incorporated Floating gate memory cell and device
US4964080A (en) * 1990-03-09 1990-10-16 Intel Corporation Three-dimensional memory cell with integral select transistor
US5276343A (en) * 1990-04-21 1994-01-04 Kabushiki Kaisha Toshiba Semiconductor memory device having a bit line constituted by a semiconductor layer
JPH0834302B2 (ja) * 1990-04-21 1996-03-29 株式会社東芝 半導体記憶装置
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5122848A (en) * 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5229310A (en) * 1991-05-03 1993-07-20 Motorola, Inc. Method for making a self-aligned vertical thin-film transistor in a semiconductor device
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
US5670803A (en) * 1995-02-08 1997-09-23 International Business Machines Corporation Three-dimensional SRAM trench structure and fabrication method therefor
GB2347014B (en) 1999-02-18 2003-04-16 Zetex Plc Semiconductor device
US7121651B2 (en) * 2002-05-09 2006-10-17 Brother Kogyo Kabushiki Kaisha Droplet-jetting device with pressure chamber expandable by elongation of pressure-generating section
US6586291B1 (en) * 2002-08-08 2003-07-01 Lsi Logic Corporation High density memory with storage capacitor
US20090242941A1 (en) 2008-03-25 2009-10-01 International Business Machines Corporation Structure and method for manufacturing device with a v-shape channel nmosfet
FR2986106B1 (fr) * 2012-01-20 2014-08-22 Soitec Silicon On Insulator Procede de fabrication de substrats semi-conducteur, et substrats semi-conducteur
KR102721980B1 (ko) 2022-02-24 2024-10-25 삼성전자주식회사 기판 정렬 장치 및 이를 이용한 기판 정렬 방법
US12610605B2 (en) * 2022-11-28 2026-04-21 Globalfoundries U.S. Inc. IC structure with gate electrode fully within V-shaped cavity

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3975221A (en) * 1973-08-29 1976-08-17 American Micro-Systems, Inc. Low capacitance V groove MOS NOR gate and method of manufacture
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element
JPS538076A (en) * 1976-07-12 1978-01-25 Hitachi Ltd Production of mis semiconductor device
DE2642615C2 (de) * 1976-09-22 1986-04-24 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher
US4065783A (en) * 1976-10-18 1977-12-27 Paul Hsiung Ouyang Self-aligned double implanted short channel V-groove MOS device
US4116720A (en) * 1977-12-27 1978-09-26 Burroughs Corporation Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance
JPS54154977A (en) * 1978-05-29 1979-12-06 Fujitsu Ltd Semiconductor device and its manufacture
JPS5537250U (https=) * 1978-08-31 1980-03-10
US4225879A (en) * 1979-01-26 1980-09-30 Burroughs Corporation V-MOS Field effect transistor for a dynamic memory cell having improved capacitance

Also Published As

Publication number Publication date
JPH0230585B2 (https=) 1990-07-06
DE3165658D1 (en) 1984-09-27
EP0042084A1 (en) 1981-12-23
EP0042084B1 (en) 1984-08-22
US4364074A (en) 1982-12-14
JPS5713770A (en) 1982-01-23

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