US20090242941A1 - Structure and method for manufacturing device with a v-shape channel nmosfet - Google Patents
Structure and method for manufacturing device with a v-shape channel nmosfet Download PDFInfo
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- US20090242941A1 US20090242941A1 US12/054,738 US5473808A US2009242941A1 US 20090242941 A1 US20090242941 A1 US 20090242941A1 US 5473808 A US5473808 A US 5473808A US 2009242941 A1 US2009242941 A1 US 2009242941A1
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- nmosfet
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- 238000000034 method Methods 0.000 title claims description 53
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 8
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000001020 plasma etching Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 238000011065 in-situ storage Methods 0.000 claims description 9
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 8
- 229910002244 LaAlO3 Inorganic materials 0.000 claims description 4
- 229910002370 SrTiO3 Inorganic materials 0.000 claims description 4
- 229910010037 TiAlN Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052593 corundum Inorganic materials 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
- 108091006146 Channels Proteins 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L21/8232—Field-effect technology
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- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Definitions
- the present invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a structure and method for manufacturing a complementary metal-oxide-semiconductor (CMOS) with a V-shape channel nMOSFET.
- CMOS complementary metal-oxide-semiconductor
- MOSFETs metal-oxide-semiconductor field-effect transistors
- VLSI very-large-scale integration
- nMOSFET n-type channel
- pMOSFET p-type channel
- a method of forming a device includes forming an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface, wherein a top of the oxide layer is co-planar with a top of the pMOSFET region.
- the method includes patterning a hardmask nitride to cover the oxide layer above the pMOSFET region.
- the method includes removing poly-Si in the nMOSFET region.
- the method includes removing gate oxide in the nMOSFET region to expose a Si layer in a channel area of the nMOSFET region.
- the method includes removing Si to form a cavity in the channel area of the nMOSFET region.
- the method includes performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane.
- the method includes removing the hardmask nitride above the pMOSFET region.
- the method includes depositing an nMOSFET gate dielectric layer.
- the method includes depositing an nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer.
- the method includes depositing poly-Si on top of the nMOSFET metal gate layer, such that a top surface of the Poly-Si is below the top of the oxide layer.
- the method further includes removing a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top surface of the oxide layer.
- the method also includes removing the oxide layer.
- a method of forming a device includes depositing an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface.
- the method includes performing a chemical mechanical polish (CMP) of the oxide layer.
- CMP chemical mechanical polish
- the method includes patterning a hardmask nitride to cover the oxide layer above the pMOSFET region.
- the method includes performing a first reactive ion etching (RIE) to remove poly-Si in the nMOSFET region.
- the method includes performing a second RIE to remove gate oxide in the nMOSFET region and to expose a Si layer in a channel area of the nMOSFET region.
- RIE reactive ion etching
- the method includes performing a third RIE to remove Si to form a cavity in the channel area of the nMOSFET region, wherein the cavity has a depth less than the thickness of the Si layer.
- the method includes performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane.
- the method includes removing the hardmask nitride above the pMOSFET region.
- the method includes depositing an nMOSFET gate dielectric layer.
- the method includes depositing an nMOSFET metal gate layer.
- the method includes etching back a portion of the nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer.
- the method includes depositing in-situ doped poly-Si on top of the nMOSFET metal gate layer.
- the method includes etching back a portion the in-situ doped poly-Si, such that a top surface of the in-situ doped poly-Si is below the top of the oxide layer.
- the method further includes etching back a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top of the oxide layer.
- the method also includes etching back the oxide layer.
- a device in a further aspect of the invention, includes a CMOS structure having an nMOSFET region and a pMOSFET region.
- the device includes a V-shape surface in the nMOSFET region, the V-shape surface having an orientation in a (100) plane and extending into a Si layer in the nMOSFET region.
- the device includes a gate dielectric layer in the V-shape surface.
- the device further includes a metal gate layer on top of the gate dielectric layer.
- the device also includes poly-Si on top of the metal gate layer.
- FIG. 1 shows a starting structure and processing steps in accordance with an embodiment of the invention
- FIGS. 2-9 show processing steps and intermediate structures in accordance with an embodiment of the invention.
- FIG. 10 shows processing steps and a final structure in accordance with an embodiment of the invention.
- the invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a structure and method for manufacturing a device with a V-shape channel nMOSFET.
- FIG. 1 shows a starting structure and processing steps in accordance with an embodiment of the invention.
- a CMOS structure is built with conventional process flow on a (110) silicon surface on Si layer 100 . All necessary implantation have been finished, such as halo, extension and source/drain.
- the structure includes an nMOSFET region 116 and a pMOSFET region 118 . Nitride spacers 190 are formed.
- Gate oxide 160 is deposited on top of a Si layer 100 .
- Poly-Si 180 is deposited on gate oxide 160 .
- a shallow trench isolation region 120 is formed in Si layer 100 .
- the gate length of the nMOSFET may be different from the pMOSFET.
- an oxide layer 220 is deposited on top of the nitride spacer 190 and Si layer 100 .
- a top of the oxide layer 220 is co-planar with a top of the pMOSFET region.
- a chemical mechanical polish (CMP) of oxide layer 220 may be performed on the top of nitride spacer 190 to make it co-planar.
- a hardmask nitride 240 is patterned to cover the pMOSFET region 118 .
- Poly-Si 180 is removed in the nMOSFET region 116 .
- Reactive ion etching (RIE) may be performed to remove poly-Si 180 .
- Gate oxide 160 is removed in the nMOSFET region 116 and to expose an Si layer 100 in a channel area of the nMOSFET region 116 .
- RIE may also be performed to remove gate oxide 160 to expose Si layer 100 in the channel area of nMOSFET region 116 .
- Si is removed in the nMOSFET region 116 to form a cavity 260 in the nMOSFET channel area.
- RIE may also be performed to remove Si to form the cavity in the nMOSFET channel area.
- Cavity 260 has a depth less than the thickness of Si layer 100 .
- V-shape surface 280 has an orientation in a (100) plane.
- nMOSFET gate dielectric layer 300 is deposited.
- the nMOSFET gate dielectric layer 300 may be a high-k material such as, for example, HfO2, ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 or LaAlO 3 .
- An nMOSFET metal gate layer 320 is also deposited.
- the nMOSFET metal gate layer may include, for example, TaN, TiN, TiAlN or WN.
- the nMOSFET metal gate layer 320 is partially removed.
- the nMOSFET metal gate layer 320 may be etched back using conventional processes such that a top surface of nMOSFET metal gate layer 320 is below a top of oxide layer 220 .
- Poly-Si 340 may be in-situ doped. Specifically, poly-Si 340 may be doped with P.
- a portion of poly-Si 340 is partially removed.
- a portion of nMOSFET gate dielectric layer 300 is removed.
- Portions of poly-Si 340 and nMOSFET gate dielectric layer 300 may be etched back using conventional processes such that a top surface of nMOSFET gate dielectric layer 300 and a top surface of poly-Si 340 are below a top of oxide layer 220 .
- FIG. 10 shows processing steps and a final structure in accordance with an embodiment of the invention.
- Oxide layer 220 is removed.
- Oxide layer 220 may be etched back using conventional processes. After this step, one can follow conventional process steps to finish the CMOS device (i.e., ion implantation, source/drain activation anneal, silicide formation and metal contacts).
- CMOS device i.e., ion implantation, source/drain activation anneal, silicide formation and metal contacts.
- nMOSFET 116 is built on a (100) surface and pMOSFET 118 on a (110) surface.
- the method as described above is used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
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Abstract
Description
- The present invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a structure and method for manufacturing a complementary metal-oxide-semiconductor (CMOS) with a V-shape channel nMOSFET.
- Scaling of gate length of metal-oxide-semiconductor field-effect transistors (MOSFETs) can enhance performance. However, it increases stand-by power of very-large-scale integration (VLSI). Therefore, power consumption is a serious problem for VLSI. MOSFETs with long channel gate length have low stand-by power, but performance is relatively poor.
- Increasing of mobility of electrons or holes can enhance performance without increasing stand-by power. Mobility of electrons or holes depends on surface crystalline orientations in silicon. In a MOSFET with an n-type channel (nMOSFET), electrons are responsible for conduction. In a MOSFET with a p-type channel (pMOSFET), holes are responsible for conduction. It is desirable to build an nMOSFET in a (100) surface and pMOSFET in a (110) surface in order to obtain the maximum electron mobility for the nMOSFET and the maximum hole mobility for the pMOSFET.
- However, it is difficult and/or expensive to manufacture substrates that have hybrid surface crystalline orientations.
- In a first aspect of the invention, a method of forming a device includes forming an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface, wherein a top of the oxide layer is co-planar with a top of the pMOSFET region. The method includes patterning a hardmask nitride to cover the oxide layer above the pMOSFET region. The method includes removing poly-Si in the nMOSFET region. The method includes removing gate oxide in the nMOSFET region to expose a Si layer in a channel area of the nMOSFET region. The method includes removing Si to form a cavity in the channel area of the nMOSFET region. The method includes performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane. The method includes removing the hardmask nitride above the pMOSFET region. The method includes depositing an nMOSFET gate dielectric layer. The method includes depositing an nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer. The method includes depositing poly-Si on top of the nMOSFET metal gate layer, such that a top surface of the Poly-Si is below the top of the oxide layer. The method further includes removing a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top surface of the oxide layer. The method also includes removing the oxide layer.
- In another aspect of the invention, a method of forming a device includes depositing an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface. The method includes performing a chemical mechanical polish (CMP) of the oxide layer. The method includes patterning a hardmask nitride to cover the oxide layer above the pMOSFET region. The method includes performing a first reactive ion etching (RIE) to remove poly-Si in the nMOSFET region. The method includes performing a second RIE to remove gate oxide in the nMOSFET region and to expose a Si layer in a channel area of the nMOSFET region. The method includes performing a third RIE to remove Si to form a cavity in the channel area of the nMOSFET region, wherein the cavity has a depth less than the thickness of the Si layer. The method includes performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane. The method includes removing the hardmask nitride above the pMOSFET region. The method includes depositing an nMOSFET gate dielectric layer. The method includes depositing an nMOSFET metal gate layer. The method includes etching back a portion of the nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer. The method includes depositing in-situ doped poly-Si on top of the nMOSFET metal gate layer. The method includes etching back a portion the in-situ doped poly-Si, such that a top surface of the in-situ doped poly-Si is below the top of the oxide layer. The method further includes etching back a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top of the oxide layer. The method also includes etching back the oxide layer.
- In a further aspect of the invention, a device includes a CMOS structure having an nMOSFET region and a pMOSFET region. The device includes a V-shape surface in the nMOSFET region, the V-shape surface having an orientation in a (100) plane and extending into a Si layer in the nMOSFET region. The device includes a gate dielectric layer in the V-shape surface. The device further includes a metal gate layer on top of the gate dielectric layer. The device also includes poly-Si on top of the metal gate layer.
- The present invention is described in the detailed description below, in reference to the accompanying drawings that depict non-limiting examples of exemplary embodiments of the present invention.
-
FIG. 1 shows a starting structure and processing steps in accordance with an embodiment of the invention; -
FIGS. 2-9 show processing steps and intermediate structures in accordance with an embodiment of the invention; and -
FIG. 10 shows processing steps and a final structure in accordance with an embodiment of the invention. - The invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a structure and method for manufacturing a device with a V-shape channel nMOSFET.
-
FIG. 1 shows a starting structure and processing steps in accordance with an embodiment of the invention. Preferably, a CMOS structure is built with conventional process flow on a (110) silicon surface onSi layer 100. All necessary implantation have been finished, such as halo, extension and source/drain. The structure includes an nMOSFETregion 116 and apMOSFET region 118.Nitride spacers 190 are formed.Gate oxide 160 is deposited on top of aSi layer 100. Poly-Si 180 is deposited ongate oxide 160. A shallowtrench isolation region 120 is formed inSi layer 100. In order to adjust the performance ratio between the nMOSFET and pMOSFET, the gate length of the nMOSFET may be different from the pMOSFET. - Referring to
FIG. 2 , anoxide layer 220 is deposited on top of thenitride spacer 190 andSi layer 100. A top of theoxide layer 220 is co-planar with a top of the pMOSFET region. A chemical mechanical polish (CMP) ofoxide layer 220 may be performed on the top ofnitride spacer 190 to make it co-planar. - Referring to
FIGS. 3 and 4 , ahardmask nitride 240 is patterned to cover thepMOSFET region 118. Poly-Si 180 is removed in thenMOSFET region 116. Reactive ion etching (RIE) may be performed to remove poly-Si 180.Gate oxide 160 is removed in thenMOSFET region 116 and to expose anSi layer 100 in a channel area of thenMOSFET region 116. RIE may also be performed to removegate oxide 160 to exposeSi layer 100 in the channel area ofnMOSFET region 116. - Referring to
FIG. 5 , Si is removed in thenMOSFET region 116 to form acavity 260 in the nMOSFET channel area. RIE may also be performed to remove Si to form the cavity in the nMOSFET channel area.Cavity 260 has a depth less than the thickness ofSi layer 100. - Referring to
FIG. 6 , selective Si epitaxial growth is performed in the cavity to form a V-shape surface 280. V-shape surface 280 has an orientation in a (100) plane. - Referring to
FIG. 7 ,hardmask nitride 240 is removed using a conventional process. An nMOSFETgate dielectric layer 300 is deposited. The nMOSFETgate dielectric layer 300 may be a high-k material such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3 or LaAlO3. An nMOSFETmetal gate layer 320 is also deposited. The nMOSFET metal gate layer may include, for example, TaN, TiN, TiAlN or WN. - Referring to
FIG. 8 , the nMOSFETmetal gate layer 320 is partially removed. The nMOSFETmetal gate layer 320 may be etched back using conventional processes such that a top surface of nMOSFETmetal gate layer 320 is below a top ofoxide layer 220. Poly-Si 340 deposited on top of nMOSFETmetal gate layer 320. Poly-Si 340 may be in-situ doped. Specifically, poly-Si 340 may be doped with P. - Referring to
FIG. 9 , a portion of poly-Si 340 is partially removed. A portion of nMOSFETgate dielectric layer 300 is removed. Portions of poly-Si 340 and nMOSFETgate dielectric layer 300 may be etched back using conventional processes such that a top surface of nMOSFETgate dielectric layer 300 and a top surface of poly-Si 340 are below a top ofoxide layer 220. -
FIG. 10 shows processing steps and a final structure in accordance with an embodiment of the invention.Oxide layer 220 is removed.Oxide layer 220 may be etched back using conventional processes. After this step, one can follow conventional process steps to finish the CMOS device (i.e., ion implantation, source/drain activation anneal, silicide formation and metal contacts). In this CMOS,nMOSFET 116 is built on a (100) surface andpMOSFET 118 on a (110) surface. - The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (22)
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US12/054,738 US20090242941A1 (en) | 2008-03-25 | 2008-03-25 | Structure and method for manufacturing device with a v-shape channel nmosfet |
US12/488,783 US20090256213A1 (en) | 2008-03-25 | 2009-06-22 | Structure and method for manufacturing device with a v-shape channel nmosfet |
US13/015,875 US8232155B2 (en) | 2008-03-25 | 2011-01-28 | Structure and method for manufacturing device with a V-shape channel nMOSFET |
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US12/054,738 US20090242941A1 (en) | 2008-03-25 | 2008-03-25 | Structure and method for manufacturing device with a v-shape channel nmosfet |
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US12/488,783 Abandoned US20090256213A1 (en) | 2008-03-25 | 2009-06-22 | Structure and method for manufacturing device with a v-shape channel nmosfet |
US13/015,875 Expired - Fee Related US8232155B2 (en) | 2008-03-25 | 2011-01-28 | Structure and method for manufacturing device with a V-shape channel nMOSFET |
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US10103226B2 (en) | 2012-04-30 | 2018-10-16 | International Business Machines Corporation | Method of fabricating tunnel transistors with abrupt junctions |
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US5571376A (en) * | 1994-03-31 | 1996-11-05 | Sharp Kabushiki Kaisha | Quantum device and method of making such a device |
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US10103226B2 (en) | 2012-04-30 | 2018-10-16 | International Business Machines Corporation | Method of fabricating tunnel transistors with abrupt junctions |
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US20090256213A1 (en) | 2009-10-15 |
US20110124165A1 (en) | 2011-05-26 |
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