CA1048653A - Method and structure for controlling carrier lifetime in semiconductor devices - Google Patents

Method and structure for controlling carrier lifetime in semiconductor devices

Info

Publication number
CA1048653A
CA1048653A CA76258550A CA258550A CA1048653A CA 1048653 A CA1048653 A CA 1048653A CA 76258550 A CA76258550 A CA 76258550A CA 258550 A CA258550 A CA 258550A CA 1048653 A CA1048653 A CA 1048653A
Authority
CA
Canada
Prior art keywords
region
atoms
implanted
regions
inert
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA76258550A
Other languages
English (en)
French (fr)
Inventor
Peter Burr
Richard C. Joy
James F. Ziegler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1048653A publication Critical patent/CA1048653A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/904—Charge carrier lifetime control

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
CA76258550A 1975-08-07 1976-08-06 Method and structure for controlling carrier lifetime in semiconductor devices Expired CA1048653A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/602,710 US4053925A (en) 1975-08-07 1975-08-07 Method and structure for controllng carrier lifetime in semiconductor devices

Publications (1)

Publication Number Publication Date
CA1048653A true CA1048653A (en) 1979-02-13

Family

ID=24412483

Family Applications (1)

Application Number Title Priority Date Filing Date
CA76258550A Expired CA1048653A (en) 1975-08-07 1976-08-06 Method and structure for controlling carrier lifetime in semiconductor devices

Country Status (14)

Country Link
US (1) US4053925A (enExample)
JP (2) JPS5221775A (enExample)
AU (1) AU501673B2 (enExample)
BE (1) BE843794A (enExample)
CA (1) CA1048653A (enExample)
CH (1) CH600571A5 (enExample)
DE (1) DE2634500A1 (enExample)
ES (1) ES450165A1 (enExample)
FR (1) FR2320636A1 (enExample)
GB (1) GB1492367A (enExample)
IT (1) IT1063768B (enExample)
NL (1) NL7608644A (enExample)
SE (1) SE415062B (enExample)
ZA (1) ZA764477B (enExample)

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US4193079A (en) * 1978-01-30 1980-03-11 Xerox Corporation MESFET with non-uniform doping
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JPS5939904B2 (ja) * 1978-09-28 1984-09-27 株式会社東芝 半導体装置
US4274105A (en) * 1978-12-29 1981-06-16 International Business Machines Corporation MOSFET Substrate sensitivity control
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US4249962A (en) * 1979-09-11 1981-02-10 Western Electric Company, Inc. Method of removing contaminating impurities from device areas in a semiconductor wafer
US4318750A (en) * 1979-12-28 1982-03-09 Westinghouse Electric Corp. Method for radiation hardening semiconductor devices and integrated circuits to latch-up effects
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US4300152A (en) * 1980-04-07 1981-11-10 Bell Telephone Laboratories, Incorporated Complementary field-effect transistor integrated circuit device
US4432008A (en) * 1980-07-21 1984-02-14 The Board Of Trustees Of The Leland Stanford Junior University Gold-doped IC resistor region
JPS5814538A (ja) * 1981-07-17 1983-01-27 Fujitsu Ltd 半導体装置の製造方法
US4412868A (en) * 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
FR2534415A1 (fr) * 1982-10-07 1984-04-13 Cii Honeywell Bull Procede de fabrication de resistances electriques dans un materiau semi-conducteur polycristallin et dispositif a circuits integres resultant
US4716451A (en) * 1982-12-10 1987-12-29 Rca Corporation Semiconductor device with internal gettering region
JPS6031232A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
US4633289A (en) * 1983-09-12 1986-12-30 Hughes Aircraft Company Latch-up immune, multiple retrograde well high density CMOS FET
US4710477A (en) * 1983-09-12 1987-12-01 Hughes Aircraft Company Method for forming latch-up immune, multiple retrograde well high density CMOS FET
GB2171555A (en) * 1985-02-20 1986-08-28 Philips Electronic Associated Bipolar semiconductor device with implanted recombination region
JPS61264751A (ja) * 1985-05-17 1986-11-22 Nippon Telegr & Teleph Corp <Ntt> 相補性ｍｉｓ型電界効果トランジスタ装置
US4689667A (en) * 1985-06-11 1987-08-25 Fairchild Semiconductor Corporation Method of controlling dopant diffusion and dopant electrical activation by implanted inert gas atoms
US4806498A (en) * 1985-06-21 1989-02-21 Texas Instruments Incorporated Semiconductor charge-coupled device and process of fabrication thereof
US4701775A (en) * 1985-10-21 1987-10-20 Motorola, Inc. Buried n- channel implant for NMOS transistors
JPS62219636A (ja) * 1986-03-20 1987-09-26 Hitachi Ltd 半導体装置
JPS63254762A (ja) * 1987-04-13 1988-10-21 Nissan Motor Co Ltd Ｃｍｏｓ半導体装置
JPH0821678B2 (ja) * 1987-05-29 1996-03-04 日産自動車株式会社 半導体装置
US4881107A (en) * 1987-07-03 1989-11-14 Nissan Motor Company, Ltd. IC device having a vertical MOSFET and an auxiliary component
US5102810A (en) * 1990-03-13 1992-04-07 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
US5097308A (en) * 1990-03-13 1992-03-17 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
US5554883A (en) * 1990-04-28 1996-09-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method therefor
JPH05198666A (ja) * 1991-11-20 1993-08-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5384477A (en) * 1993-03-09 1995-01-24 National Semiconductor Corporation CMOS latchup suppression by localized minority carrier lifetime reduction
US5358879A (en) * 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
JPH09502303A (ja) * 1993-09-03 1997-03-04 ナショナル・セミコンダクター・コーポレイション マイクロエレクトロニクスの製造に使用するための平坦な分離方法
JP3135762B2 (ja) * 1993-10-29 2001-02-19 株式会社東芝 半導体集積回路装置
US5508211A (en) * 1994-02-17 1996-04-16 Lsi Logic Corporation Method of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
JPH07335870A (ja) * 1994-06-14 1995-12-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
EP0694960B1 (en) * 1994-07-25 2002-07-03 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Process for the localized reduction of the lifetime of charge carriers
US5747371A (en) * 1996-07-22 1998-05-05 Motorola, Inc. Method of manufacturing vertical MOSFET
US6410409B1 (en) * 1996-10-31 2002-06-25 Advanced Micro Devices, Inc. Implanted barrier layer for retarding upward diffusion of substrate dopant
US6455903B1 (en) * 2000-01-26 2002-09-24 Advanced Micro Devices, Inc. Dual threshold voltage MOSFET by local confinement of channel depletion layer using inert ion implantation
DE10061191A1 (de) * 2000-12-08 2002-06-13 Ihp Gmbh Schichten in Substratscheiben
US20040176483A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Cellular materials formed using surface transformation
US6836134B2 (en) * 2002-06-11 2004-12-28 Delphi Technologies, Inc. Apparatus and method for determining leakage current between a first semiconductor region and a second semiconductor region to be formed therein
DE10261307B4 (de) * 2002-12-27 2010-11-11 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Spannungsoberflächenschicht in einem Halbleiterelement
US7501329B2 (en) * 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7662701B2 (en) * 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation
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Also Published As

Publication number Publication date
GB1492367A (en) 1977-11-16
DE2634500A1 (de) 1977-02-17
SE7608635L (sv) 1977-02-08
FR2320636B1 (enExample) 1978-05-19
ZA764477B (en) 1978-03-29
JPS5942464B2 (ja) 1984-10-15
FR2320636A1 (fr) 1977-03-04
JPS5221775A (en) 1977-02-18
SE415062B (sv) 1980-09-01
JPS57118667A (en) 1982-07-23
AU1665476A (en) 1978-02-09
JPS5723425B2 (enExample) 1982-05-18
ES450165A1 (es) 1977-06-16
IT1063768B (it) 1985-02-11
BE843794A (fr) 1976-11-03
CH600571A5 (enExample) 1978-06-15
AU501673B2 (en) 1979-06-28
NL7608644A (nl) 1977-02-09
US4053925A (en) 1977-10-11

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