BRPI0917642A2 - esquema de potência dual em circuito de memória. - Google Patents
esquema de potência dual em circuito de memória.Info
- Publication number
- BRPI0917642A2 BRPI0917642A2 BRPI0917642A BRPI0917642A BRPI0917642A2 BR PI0917642 A2 BRPI0917642 A2 BR PI0917642A2 BR PI0917642 A BRPI0917642 A BR PI0917642A BR PI0917642 A BRPI0917642 A BR PI0917642A BR PI0917642 A2 BRPI0917642 A2 BR PI0917642A2
- Authority
- BR
- Brazil
- Prior art keywords
- memory circuit
- dual power
- power scheme
- scheme
- dual
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/192,561 US8139426B2 (en) | 2008-08-15 | 2008-08-15 | Dual power scheme in memory circuit |
| PCT/US2009/053870 WO2010019868A1 (en) | 2008-08-15 | 2009-08-14 | Dual power scheme in memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BRPI0917642A2 true BRPI0917642A2 (pt) | 2015-11-17 |
Family
ID=41134654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BRPI0917642A BRPI0917642A2 (pt) | 2008-08-15 | 2009-08-14 | esquema de potência dual em circuito de memória. |
Country Status (13)
| Country | Link |
|---|---|
| US (1) | US8139426B2 (pt) |
| EP (1) | EP2329498B1 (pt) |
| JP (1) | JP5518864B2 (pt) |
| KR (1) | KR101383190B1 (pt) |
| CN (1) | CN102113056B (pt) |
| BR (1) | BRPI0917642A2 (pt) |
| CA (1) | CA2730457C (pt) |
| ES (1) | ES2702456T3 (pt) |
| HU (1) | HUE040309T2 (pt) |
| MX (1) | MX2011001689A (pt) |
| RU (1) | RU2480850C2 (pt) |
| TW (1) | TWI428928B (pt) |
| WO (1) | WO2010019868A1 (pt) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8429498B1 (en) * | 2009-03-25 | 2013-04-23 | Apple Inc. | Dual ECC decoder |
| US8345490B2 (en) | 2010-06-23 | 2013-01-01 | International Business Machines Corporation | Split voltage level restore and evaluate clock signals for memory address decoding |
| US8599642B2 (en) | 2010-06-23 | 2013-12-03 | International Business Machines Corporation | Port enable signal generation for gating a memory array device output |
| US8345497B2 (en) | 2010-06-23 | 2013-01-01 | International Business Machines Corporation | Internal bypassing of memory array devices |
| US8351278B2 (en) | 2010-06-23 | 2013-01-08 | International Business Machines Corporation | Jam latch for latching memory array output data |
| US8995207B2 (en) * | 2011-08-12 | 2015-03-31 | Qualcomm Incorporated | Data storage for voltage domain crossings |
| US9064559B2 (en) | 2013-08-15 | 2015-06-23 | Arm Limited | Memory device and method of performing access operations within such a memory device |
| CN103794243B (zh) * | 2014-02-28 | 2016-08-17 | 北京航空航天大学 | 一种磁性位单元双电压写入方法 |
| US9070433B1 (en) | 2014-03-11 | 2015-06-30 | International Business Machines Corporation | SRAM supply voltage global bitline precharge pulse |
| US9595307B2 (en) | 2014-05-22 | 2017-03-14 | Samsung Electronics Co., Ltd. | Volatile memory device and system-on-chip including the same |
| US10084481B2 (en) | 2014-12-18 | 2018-09-25 | Apple Inc. | GLDPC soft decoding with hard decision inputs |
| US9418716B1 (en) | 2015-04-15 | 2016-08-16 | Qualcomm Incorporated | Word line and bit line tracking across diverse power domains |
| US9595332B2 (en) * | 2015-06-15 | 2017-03-14 | Cypress Semiconductor Corporation | High speed, high voltage tolerant circuits in flash path |
| US9515075B1 (en) | 2015-08-31 | 2016-12-06 | Cypress Semiconductor Corporation | Method for fabricating ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier |
| US9449655B1 (en) | 2015-08-31 | 2016-09-20 | Cypress Semiconductor Corporation | Low standby power with fast turn on for non-volatile memory devices |
| US10020048B2 (en) | 2015-12-30 | 2018-07-10 | Samsung Electronics Co., Ltd. | Integrated circuit including embedded memory device for performing dual-transient word line assist using triple power source and device having the same |
| US10848182B2 (en) | 2018-09-13 | 2020-11-24 | Apple Inc. | Iterative decoding with early termination criterion that permits errors in redundancy part |
| US11594276B2 (en) * | 2019-05-19 | 2023-02-28 | Synopsys, Inc. | Self-adjustable self-timed dual-rail SRAM |
| US11961554B2 (en) * | 2020-01-31 | 2024-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shared power footer circuit |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8902820A (nl) * | 1989-11-15 | 1991-06-03 | Philips Nv | Geintegreerde halfgeleiderschakeling van het master slice type. |
| JPH07254275A (ja) | 1994-01-31 | 1995-10-03 | Toshiba Corp | 半導体記憶装置 |
| US7106318B1 (en) * | 2000-04-28 | 2006-09-12 | Jps Group Holdings, Ltd. | Low power LCD driving scheme employing two or more power supplies |
| JP4748841B2 (ja) * | 2000-10-24 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2003132683A (ja) * | 2001-10-23 | 2003-05-09 | Hitachi Ltd | 半導体装置 |
| US6621745B1 (en) * | 2002-06-18 | 2003-09-16 | Atmel Corporation | Row decoder circuit for use in programming a memory device |
| JP2005025907A (ja) * | 2003-07-03 | 2005-01-27 | Hitachi Ltd | 半導体集積回路装置 |
| JP4373154B2 (ja) * | 2003-07-18 | 2009-11-25 | 株式会社半導体エネルギー研究所 | メモリ回路およびそのメモリ回路を有する表示装置、電子機器 |
| JP4632287B2 (ja) * | 2003-10-06 | 2011-02-16 | 株式会社日立製作所 | 半導体集積回路装置 |
| US7020041B2 (en) * | 2003-12-18 | 2006-03-28 | Intel Corporation | Method and apparatus to clamp SRAM supply voltage |
| US7042776B2 (en) * | 2004-02-18 | 2006-05-09 | International Business Machines Corporation | Method and circuit for dynamic read margin control of a memory array |
| US7345946B1 (en) * | 2004-09-24 | 2008-03-18 | Cypress Semiconductor Corporation | Dual-voltage wordline drive circuit with two stage discharge |
| KR100670682B1 (ko) * | 2005-02-04 | 2007-01-17 | 주식회사 하이닉스반도체 | 반도체 기억 소자에서의 데이터 출력 회로 및 방법 |
| JP2007035091A (ja) * | 2005-07-22 | 2007-02-08 | Sony Corp | 半導体記憶装置 |
-
2008
- 2008-08-15 US US12/192,561 patent/US8139426B2/en active Active
-
2009
- 2009-08-14 TW TW098127477A patent/TWI428928B/zh active
- 2009-08-14 KR KR1020117006003A patent/KR101383190B1/ko active IP Right Grant
- 2009-08-14 MX MX2011001689A patent/MX2011001689A/es not_active Application Discontinuation
- 2009-08-14 BR BRPI0917642A patent/BRPI0917642A2/pt not_active Application Discontinuation
- 2009-08-14 JP JP2011523191A patent/JP5518864B2/ja active Active
- 2009-08-14 RU RU2011109561/08A patent/RU2480850C2/ru active
- 2009-08-14 CN CN2009801302684A patent/CN102113056B/zh active Active
- 2009-08-14 ES ES09791532T patent/ES2702456T3/es active Active
- 2009-08-14 CA CA2730457A patent/CA2730457C/en active Active
- 2009-08-14 HU HUE09791532A patent/HUE040309T2/hu unknown
- 2009-08-14 WO PCT/US2009/053870 patent/WO2010019868A1/en active Application Filing
- 2009-08-14 EP EP09791532.6A patent/EP2329498B1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010019868A1 (en) | 2010-02-18 |
| ES2702456T3 (es) | 2019-03-01 |
| JP2012500445A (ja) | 2012-01-05 |
| JP5518864B2 (ja) | 2014-06-11 |
| CN102113056A (zh) | 2011-06-29 |
| US8139426B2 (en) | 2012-03-20 |
| MX2011001689A (es) | 2011-04-07 |
| CA2730457A1 (en) | 2010-02-18 |
| TW201015575A (en) | 2010-04-16 |
| EP2329498A1 (en) | 2011-06-08 |
| TWI428928B (zh) | 2014-03-01 |
| CA2730457C (en) | 2014-09-02 |
| HUE040309T2 (hu) | 2019-02-28 |
| US20100039872A1 (en) | 2010-02-18 |
| KR101383190B1 (ko) | 2014-04-09 |
| RU2480850C2 (ru) | 2013-04-27 |
| CN102113056B (zh) | 2013-11-20 |
| KR20110055649A (ko) | 2011-05-25 |
| EP2329498B1 (en) | 2018-09-19 |
| RU2011109561A (ru) | 2012-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
| B06T | Formal requirements before examination [chapter 6.20 patent gazette] | ||
| B07A | Application suspended after technical examination (opinion) [chapter 7.1 patent gazette] | ||
| B09B | Patent application refused [chapter 9.2 patent gazette] | ||
| B12B | Appeal against refusal [chapter 12.2 patent gazette] |