BR9909295A - Estrutura de cache compartilhado para instruções temporais e não-temporais - Google Patents
Estrutura de cache compartilhado para instruções temporais e não-temporaisInfo
- Publication number
- BR9909295A BR9909295A BR9909295-6A BR9909295A BR9909295A BR 9909295 A BR9909295 A BR 9909295A BR 9909295 A BR9909295 A BR 9909295A BR 9909295 A BR9909295 A BR 9909295A
- Authority
- BR
- Brazil
- Prior art keywords
- temporal
- cache
- statements
- shared cache
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Patente de Invenção: <B>"ESTRUTURA DE CACHE COMPARTILHADO PARA INSTRUçõES TEMPORAIS E NãO TEMPORAIS"<D>. Um método e um sistema para a provisão de gerenciamento de uma memória de cache. O sistema compreende uma memória principal (11), um processador acoplado à memória principal, e pelo menos uma memória de cache (50) acoplada ao processador, para o armazenamento de forma intermediária de dados. A pelo menos uma memória de cache tem pelo menos duas vias de cache (50), cada uma compreendendo uma pluralidade de regulagens (50). Cada uma da pluralidade de regulagens tem um bit (50), o qual indica se pelo menos uma das duas vias de cache contém um dado não-temporal. O processador acessa dados a partir de uma dentre a memória principal ou a pelo menos uma memória de cache.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/053,386 US6202129B1 (en) | 1998-03-31 | 1998-03-31 | Shared cache structure for temporal and non-temporal information using indicative bits |
PCT/US1999/006501 WO1999050752A1 (en) | 1998-03-31 | 1999-03-24 | Shared cache structure for temporal and non-temporal instructions |
Publications (1)
Publication Number | Publication Date |
---|---|
BR9909295A true BR9909295A (pt) | 2000-12-05 |
Family
ID=21983863
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR9909295-6A BR9909295A (pt) | 1998-03-31 | 1999-03-24 | Estrutura de cache compartilhado para instruções temporais e não-temporais |
Country Status (10)
Country | Link |
---|---|
US (2) | US6202129B1 (pt) |
EP (1) | EP1066566B1 (pt) |
JP (1) | JP4486750B2 (pt) |
KR (1) | KR100389549B1 (pt) |
CN (1) | CN1230750C (pt) |
AU (1) | AU3364599A (pt) |
BR (1) | BR9909295A (pt) |
RU (1) | RU2212704C2 (pt) |
TW (1) | TW573252B (pt) |
WO (1) | WO1999050752A1 (pt) |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5978379A (en) * | 1997-01-23 | 1999-11-02 | Gadzoox Networks, Inc. | Fiber channel learning bridge, learning half bridge, and protocol |
US6202129B1 (en) * | 1998-03-31 | 2001-03-13 | Intel Corporation | Shared cache structure for temporal and non-temporal information using indicative bits |
US6216215B1 (en) | 1998-04-02 | 2001-04-10 | Intel Corporation | Method and apparatus for senior loads |
US6542966B1 (en) * | 1998-07-16 | 2003-04-01 | Intel Corporation | Method and apparatus for managing temporal and non-temporal data in a single cache structure |
US7430171B2 (en) | 1998-11-19 | 2008-09-30 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US6560677B1 (en) * | 1999-05-04 | 2003-05-06 | International Business Machines Corporation | Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory |
US6728835B1 (en) * | 2000-08-30 | 2004-04-27 | Unisys Corporation | Leaky cache mechanism |
US6681295B1 (en) * | 2000-08-31 | 2004-01-20 | Hewlett-Packard Development Company, L.P. | Fast lane prefetching |
US6668307B1 (en) * | 2000-09-29 | 2003-12-23 | Sun Microsystems, Inc. | System and method for a software controlled cache |
WO2002027498A2 (en) * | 2000-09-29 | 2002-04-04 | Sun Microsystems, Inc. | System and method for identifying and managing streaming-data |
US6578111B1 (en) * | 2000-09-29 | 2003-06-10 | Sun Microsystems, Inc. | Cache memory system and method for managing streaming-data |
US6598124B1 (en) * | 2000-09-29 | 2003-07-22 | Sun Microsystems, Inc. | System and method for identifying streaming-data |
US6766413B2 (en) * | 2001-03-01 | 2004-07-20 | Stratus Technologies Bermuda Ltd. | Systems and methods for caching with file-level granularity |
US7287649B2 (en) * | 2001-05-18 | 2007-10-30 | Broadcom Corporation | System on a chip for packet processing |
US6766389B2 (en) | 2001-05-18 | 2004-07-20 | Broadcom Corporation | System on a chip for networking |
US6574708B2 (en) * | 2001-05-18 | 2003-06-03 | Broadcom Corporation | Source controlled cache allocation |
US7212534B2 (en) | 2001-07-23 | 2007-05-01 | Broadcom Corporation | Flow based congestion control |
US6823426B2 (en) * | 2001-12-20 | 2004-11-23 | Intel Corporation | System and method of data replacement in cache ways |
US7328328B2 (en) * | 2002-02-19 | 2008-02-05 | Ip-First, Llc | Non-temporal memory reference control mechanism |
US7295555B2 (en) | 2002-03-08 | 2007-11-13 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
US7114043B2 (en) * | 2002-05-15 | 2006-09-26 | Broadcom Corporation | Ambiguous virtual channels |
US7266587B2 (en) * | 2002-05-15 | 2007-09-04 | Broadcom Corporation | System having interfaces, switch, and memory bridge for CC-NUMA operation |
US7269709B2 (en) * | 2002-05-15 | 2007-09-11 | Broadcom Corporation | Memory controller configurable to allow bandwidth/latency tradeoff |
US7073030B2 (en) | 2002-05-22 | 2006-07-04 | International Business Machines Corporation | Method and apparatus providing non level one information caching using prefetch to increase a hit ratio |
US7035979B2 (en) * | 2002-05-22 | 2006-04-25 | International Business Machines Corporation | Method and apparatus for optimizing cache hit ratio in non L1 caches |
US6904501B1 (en) * | 2002-06-17 | 2005-06-07 | Silicon Graphics, Inc. | Cache memory for identifying locked and least recently used storage locations |
US7934021B2 (en) | 2002-08-29 | 2011-04-26 | Broadcom Corporation | System and method for network interfacing |
US7411959B2 (en) | 2002-08-30 | 2008-08-12 | Broadcom Corporation | System and method for handling out-of-order frames |
US7346701B2 (en) | 2002-08-30 | 2008-03-18 | Broadcom Corporation | System and method for TCP offload |
US7313623B2 (en) | 2002-08-30 | 2007-12-25 | Broadcom Corporation | System and method for TCP/IP offload independent of bandwidth delay product |
US8180928B2 (en) | 2002-08-30 | 2012-05-15 | Broadcom Corporation | Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney |
US7512498B2 (en) * | 2002-12-31 | 2009-03-31 | Intel Corporation | Streaming processing of biological sequence matching |
JP4008946B2 (ja) * | 2003-11-18 | 2007-11-14 | 松下電器産業株式会社 | キャッシュメモリ及びその制御方法 |
US7321954B2 (en) * | 2004-08-11 | 2008-01-22 | International Business Machines Corporation | Method for software controllable dynamically lockable cache line replacement system |
US20060101208A1 (en) * | 2004-11-09 | 2006-05-11 | Intel Corporation | Method and apparatus for handling non-temporal memory accesses in a cache |
US7356650B1 (en) * | 2005-06-17 | 2008-04-08 | Unisys Corporation | Cache apparatus and method for accesses lacking locality |
US7437510B2 (en) * | 2005-09-30 | 2008-10-14 | Intel Corporation | Instruction-assisted cache management for efficient use of cache and memory |
US7624257B2 (en) * | 2005-11-30 | 2009-11-24 | International Business Machines Corporation | Digital data processing apparatus having hardware multithreading support including a register set reserved for special class threads |
US20070150658A1 (en) * | 2005-12-28 | 2007-06-28 | Jaideep Moses | Pinning locks in shared cache |
US8527713B2 (en) * | 2006-01-31 | 2013-09-03 | Qualcomm Incorporated | Cache locking without interference from normal allocations |
GB0603552D0 (en) * | 2006-02-22 | 2006-04-05 | Advanced Risc Mach Ltd | Cache management within a data processing apparatus |
EP1990732A4 (en) * | 2006-02-27 | 2009-09-02 | Fujitsu Ltd | DEVICE, METHOD AND LRU CONTROL PROGRAM |
US20080147989A1 (en) * | 2006-12-14 | 2008-06-19 | Arm Limited | Lockdown control of a multi-way set associative cache memory |
US8078803B2 (en) | 2008-01-30 | 2011-12-13 | Qualcomm Incorporated | Apparatus and methods to reduce castouts in a multi-level cache hierarchy |
US7793049B2 (en) * | 2007-10-30 | 2010-09-07 | International Business Machines Corporation | Mechanism for data cache replacement based on region policies |
US8108614B2 (en) * | 2007-12-31 | 2012-01-31 | Eric Sprangle | Mechanism for effectively caching streaming and non-streaming data patterns |
DK2318935T3 (en) * | 2008-07-23 | 2015-01-26 | Micro Motion Inc | Processing system with external storage access |
US8364898B2 (en) * | 2009-01-23 | 2013-01-29 | International Business Machines Corporation | Optimizing a cache back invalidation policy |
US8312219B2 (en) * | 2009-03-02 | 2012-11-13 | International Business Machines Corporation | Hybrid caching techniques and garbage collection using hybrid caching techniques |
US9063825B1 (en) * | 2009-09-21 | 2015-06-23 | Tilera Corporation | Memory controller load balancing with configurable striping domains |
US8560777B2 (en) * | 2009-12-16 | 2013-10-15 | Telefonaktiebolaget L M Ericsson (Publ) | Method, server, computer program and computer program product for caching |
US9323527B2 (en) * | 2010-10-15 | 2016-04-26 | International Business Machines Corporation | Performance of emerging applications in a virtualized environment using transient instruction streams |
US9600416B2 (en) | 2011-09-30 | 2017-03-21 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
CN107608910B (zh) | 2011-09-30 | 2021-07-02 | 英特尔公司 | 用于实现具有不同操作模式的多级存储器分级结构的设备和方法 |
US9317429B2 (en) | 2011-09-30 | 2016-04-19 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels |
EP2761472B1 (en) | 2011-09-30 | 2020-04-01 | Intel Corporation | Memory channel that supports near memory and far memory access |
WO2013080426A1 (ja) * | 2011-12-01 | 2013-06-06 | パナソニック株式会社 | 熱を考慮した構造を持つ集積回路装置、三次元集積回路、三次元プロセッサ装置、及びプロセススケジューラ |
US9519549B2 (en) * | 2012-01-11 | 2016-12-13 | International Business Machines Corporation | Data storage backup with lessened cache pollution |
US8856455B2 (en) | 2012-03-28 | 2014-10-07 | International Business Machines Corporation | Data cache block deallocate requests |
US8874852B2 (en) | 2012-03-28 | 2014-10-28 | International Business Machines Corporation | Data cache block deallocate requests in a multi-level cache hierarchy |
CN103577480B (zh) * | 2012-08-07 | 2017-05-31 | 中国银联股份有限公司 | 一种参数划分系统及其方法、一种业务处理系统及其方法 |
US9558121B2 (en) * | 2012-12-28 | 2017-01-31 | Intel Corporation | Two-level cache locking mechanism |
US9256539B2 (en) | 2013-03-07 | 2016-02-09 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Sharing cache in a computing system |
US9311239B2 (en) | 2013-03-14 | 2016-04-12 | Intel Corporation | Power efficient level one data cache access with pre-validated tags |
US20150095586A1 (en) * | 2013-09-30 | 2015-04-02 | Advanced Micro Devices , Inc. | Storing non-temporal cache data |
US11580125B2 (en) * | 2015-05-08 | 2023-02-14 | Adp, Inc. | Information system with temporal data |
US10379827B2 (en) | 2016-12-29 | 2019-08-13 | Intel Corporation | Automatic identification and generation of non-temporal store and load operations in a dynamic optimization environment |
US11681627B1 (en) * | 2021-10-18 | 2023-06-20 | Meta Platforms Technologies, Llc | Distributed temporal cache for Systems on a Chip |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5119453A (en) * | 1974-08-08 | 1976-02-16 | Fujitsu Ltd | Patsufua memoriseigyohoshiki |
JPS5534336A (en) * | 1978-08-31 | 1980-03-10 | Fujitsu Ltd | Buffer memory control method |
JPS58159285A (ja) * | 1982-03-17 | 1983-09-21 | Nec Corp | バツフアメモリ制御方式 |
JPH01133162A (ja) * | 1987-11-18 | 1989-05-25 | Fujitsu Ltd | キャッシュメモリ制御方式 |
US4905141A (en) | 1988-10-25 | 1990-02-27 | International Business Machines Corporation | Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification |
JPH0358151A (ja) * | 1989-07-26 | 1991-03-13 | Nec Corp | キャッシュメモリ装置 |
JPH0358252A (ja) * | 1989-07-27 | 1991-03-13 | Nec Corp | キャッシュメモリ制御装置 |
JPH041838A (ja) * | 1990-04-18 | 1992-01-07 | Nec Corp | キャッシュメモリ制御回路 |
JPH04215151A (ja) * | 1990-12-13 | 1992-08-05 | Nec Commun Syst Ltd | キャッシュ制御方式 |
EP0496439B1 (en) * | 1991-01-15 | 1998-01-21 | Koninklijke Philips Electronics N.V. | Computer system with multi-buffer data cache and method therefor |
GB2255211B (en) * | 1991-04-25 | 1995-05-17 | Intel Corp | LRU pointer updating in a controller for two-way set associative cache |
GB2256512B (en) * | 1991-06-04 | 1995-03-15 | Intel Corp | Second level cache controller unit and system |
JPH05165726A (ja) * | 1991-12-12 | 1993-07-02 | Nec Corp | データ処理装置 |
JPH05233454A (ja) * | 1992-02-24 | 1993-09-10 | Hitachi Ltd | キャッシュメモリ装置 |
US5353425A (en) * | 1992-04-29 | 1994-10-04 | Sun Microsystems, Inc. | Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature |
US5471605A (en) * | 1992-08-27 | 1995-11-28 | Intel Corporation | Apparatus for updating a multi-way set associative cache memory status array |
US5434992A (en) | 1992-09-04 | 1995-07-18 | International Business Machines Corporation | Method and means for dynamically partitioning cache into a global and data type subcache hierarchy from a real time reference trace |
US5493667A (en) * | 1993-02-09 | 1996-02-20 | Intel Corporation | Apparatus and method for an instruction cache locking scheme |
JPH06348595A (ja) * | 1993-06-07 | 1994-12-22 | Hitachi Ltd | キャッシュ装置 |
JPH07281957A (ja) * | 1994-04-15 | 1995-10-27 | Hitachi Ltd | キャッシュ記憶装置およびアクセス命令生成方法 |
US5826052A (en) | 1994-04-29 | 1998-10-20 | Advanced Micro Devices, Inc. | Method and apparatus for concurrent access to multiple physical caches |
JPH07334428A (ja) * | 1994-06-14 | 1995-12-22 | Toshiba Corp | キャッシュメモリ |
US5584014A (en) * | 1994-12-20 | 1996-12-10 | Sun Microsystems, Inc. | Apparatus and method to preserve data in a set associative memory device |
US5701426A (en) * | 1995-03-31 | 1997-12-23 | Bull Information Systems Inc. | Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio |
US5845317A (en) * | 1995-11-17 | 1998-12-01 | Micron Technology, Inc. | Multi-way cache expansion circuit architecture |
GB2311880A (en) * | 1996-04-03 | 1997-10-08 | Advanced Risc Mach Ltd | Partitioned cache memory |
US5829025A (en) * | 1996-12-17 | 1998-10-27 | Intel Corporation | Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction |
JPH10207767A (ja) * | 1997-01-16 | 1998-08-07 | Toshiba Corp | ロック機能付キャッシュメモリ及びこのキャッシュメモリを備えたマイクロプロセッサ |
US6434671B2 (en) * | 1997-09-30 | 2002-08-13 | Intel Corporation | Software-controlled cache memory compartmentalization |
US6105111A (en) * | 1998-03-31 | 2000-08-15 | Intel Corporation | Method and apparatus for providing a cache management technique |
US6202129B1 (en) * | 1998-03-31 | 2001-03-13 | Intel Corporation | Shared cache structure for temporal and non-temporal information using indicative bits |
US6223258B1 (en) * | 1998-03-31 | 2001-04-24 | Intel Corporation | Method and apparatus for implementing non-temporal loads |
US6205520B1 (en) * | 1998-03-31 | 2001-03-20 | Intel Corporation | Method and apparatus for implementing non-temporal stores |
-
1998
- 1998-03-31 US US09/053,386 patent/US6202129B1/en not_active Expired - Lifetime
-
1999
- 1999-03-24 EP EP99915030A patent/EP1066566B1/en not_active Expired - Lifetime
- 1999-03-24 KR KR10-2000-7010799A patent/KR100389549B1/ko not_active IP Right Cessation
- 1999-03-24 CN CNB998047333A patent/CN1230750C/zh not_active Expired - Lifetime
- 1999-03-24 BR BR9909295-6A patent/BR9909295A/pt not_active Application Discontinuation
- 1999-03-24 WO PCT/US1999/006501 patent/WO1999050752A1/en active IP Right Grant
- 1999-03-24 RU RU2000127102/09A patent/RU2212704C2/ru not_active IP Right Cessation
- 1999-03-24 JP JP2000541596A patent/JP4486750B2/ja not_active Expired - Fee Related
- 1999-03-24 AU AU33645/99A patent/AU3364599A/en not_active Abandoned
- 1999-03-31 TW TW88105070A patent/TW573252B/zh not_active IP Right Cessation
-
2001
- 2001-03-09 US US09/803,357 patent/US6584547B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP4486750B2 (ja) | 2010-06-23 |
EP1066566A4 (en) | 2002-10-23 |
US20020007441A1 (en) | 2002-01-17 |
TW573252B (en) | 2004-01-21 |
EP1066566B1 (en) | 2006-11-02 |
CN1295687A (zh) | 2001-05-16 |
EP1066566A1 (en) | 2001-01-10 |
AU3364599A (en) | 1999-10-18 |
US6584547B2 (en) | 2003-06-24 |
JP2002510085A (ja) | 2002-04-02 |
RU2212704C2 (ru) | 2003-09-20 |
CN1230750C (zh) | 2005-12-07 |
KR20010042262A (ko) | 2001-05-25 |
WO1999050752A9 (en) | 2000-05-25 |
WO1999050752A1 (en) | 1999-10-07 |
KR100389549B1 (ko) | 2003-06-27 |
US6202129B1 (en) | 2001-03-13 |
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