DE69935491D1 - Zweistufiges, nicht-blockierendes, überlappend arbeitendes Cachesystem das Zugangskollisionen automatisch verhindert - Google Patents

Zweistufiges, nicht-blockierendes, überlappend arbeitendes Cachesystem das Zugangskollisionen automatisch verhindert

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Publication number
DE69935491D1
DE69935491D1 DE69935491T DE69935491T DE69935491D1 DE 69935491 D1 DE69935491 D1 DE 69935491D1 DE 69935491 T DE69935491 T DE 69935491T DE 69935491 T DE69935491 T DE 69935491T DE 69935491 D1 DE69935491 D1 DE 69935491D1
Authority
DE
Germany
Prior art keywords
blocking
level
cache system
prevents access
automatically prevents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69935491T
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English (en)
Inventor
Nicholas J Richardson
Charles A Stack
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE69935491D1 publication Critical patent/DE69935491D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69935491T 1998-12-04 1999-12-01 Zweistufiges, nicht-blockierendes, überlappend arbeitendes Cachesystem das Zugangskollisionen automatisch verhindert Expired - Lifetime DE69935491D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/205,598 US6519682B2 (en) 1998-12-04 1998-12-04 Pipelined non-blocking level two cache system with inherent transaction collision-avoidance

Publications (1)

Publication Number Publication Date
DE69935491D1 true DE69935491D1 (de) 2007-04-26

Family

ID=22762852

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69935491T Expired - Lifetime DE69935491D1 (de) 1998-12-04 1999-12-01 Zweistufiges, nicht-blockierendes, überlappend arbeitendes Cachesystem das Zugangskollisionen automatisch verhindert

Country Status (3)

Country Link
US (1) US6519682B2 (de)
EP (1) EP1006448B1 (de)
DE (1) DE69935491D1 (de)

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Also Published As

Publication number Publication date
US6519682B2 (en) 2003-02-11
EP1006448A1 (de) 2000-06-07
US20020069326A1 (en) 2002-06-06
EP1006448B1 (de) 2007-03-14

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