BR9903228A - Sistema de processamento de dados de acesso de memória não-uniforme (numa) que armazena temporariamente potenciais transações de terceiro nó para reduzir a latência de comunicação - Google Patents

Sistema de processamento de dados de acesso de memória não-uniforme (numa) que armazena temporariamente potenciais transações de terceiro nó para reduzir a latência de comunicação

Info

Publication number
BR9903228A
BR9903228A BR9903228-7A BR9903228A BR9903228A BR 9903228 A BR9903228 A BR 9903228A BR 9903228 A BR9903228 A BR 9903228A BR 9903228 A BR9903228 A BR 9903228A
Authority
BR
Brazil
Prior art keywords
processing node
transaction
interconnection
memory access
memory
Prior art date
Application number
BR9903228-7A
Other languages
English (en)
Inventor
Gary Dale Carpenter
Mark Edward Dean
David Brian Glasco
Richard Nicholas Iachetta Jr
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9903228A publication Critical patent/BR9903228A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

Patente de Invenção: <B>"SISTEMA DE PROCESSAMENTO DE DADOS DE ACESSO DE MEMóRIA NãO-UNIFORME (NUMA) QUE ARMAZENA TEMPORARIAMENTE POTENCIAIS TRANSAçõES DE TERCEIRO Nó PARA REDUZIR A LATêNCIA DE COMUNICAçãO"<D>. Trata-se de um sistema de computador de acesso de memória não-uniforme (NUMA) incluindo uma interligação à qual se encontram acoplados múltiplos nós de processamento (incluindo um primeiro, um segundo, e um terceiro nós de processamento). Cada um dos primeiro, segundo, e terceiro nós de processamento inclui pelo menos um processador e uma memória de sistema local. O sistema de computador NUMA inclui adicionalmente uma memória de armazenamento temporário de transações, acoplada à interligação, que armazena transações de comunicação transmitidas através da interligação que são tanto iniciadas por, quanto destinadas para, um nó de processamento diverso do terceiro nó de processamento. Em resposta a uma determinação de que uma transação de comunicação em particular tendo originalmente como alvo um outro nó de processamento deverá ser processada pelo terceiro nó de processamento, a lógica de controle de armazenamento temporário acoplada à memória de armazenamento temporário de transações faz a transação de comunicação em particular ser recuperada da memória de armazenamento temporário de transações e ser processada pelo terceiro nó de processamento. Numa configuração, a interligação inclui uma textura de difusão, e a memória de armazenamento temporário de transações e a lógica de controle de armazenamento temporário formam uma parte do terceiro nó de processamento.
BR9903228-7A 1998-06-30 1999-06-30 Sistema de processamento de dados de acesso de memória não-uniforme (numa) que armazena temporariamente potenciais transações de terceiro nó para reduzir a latência de comunicação BR9903228A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/106,945 US6067611A (en) 1998-06-30 1998-06-30 Non-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latency

Publications (1)

Publication Number Publication Date
BR9903228A true BR9903228A (pt) 2000-10-03

Family

ID=22314080

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9903228-7A BR9903228A (pt) 1998-06-30 1999-06-30 Sistema de processamento de dados de acesso de memória não-uniforme (numa) que armazena temporariamente potenciais transações de terceiro nó para reduzir a latência de comunicação

Country Status (5)

Country Link
US (1) US6067611A (pt)
JP (1) JP3470951B2 (pt)
KR (1) KR100324975B1 (pt)
BR (1) BR9903228A (pt)
CA (1) CA2271536C (pt)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6546429B1 (en) * 1998-09-21 2003-04-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry
US6418462B1 (en) * 1999-01-07 2002-07-09 Yongyong Xu Global sideband service distributed computing method
US6192452B1 (en) * 1999-02-26 2001-02-20 International Business Machines Corporation Method and system for avoiding data loss due to cancelled transactions within a non-uniform memory access system
US6591348B1 (en) * 1999-09-09 2003-07-08 International Business Machines Corporation Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system
US6591307B1 (en) * 1999-11-09 2003-07-08 International Business Machines Corporation Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response
JP3764015B2 (ja) * 1999-12-13 2006-04-05 富士通株式会社 メモリアクセス方法及びマルチプロセッサシステム
KR100362607B1 (ko) * 2000-05-10 2002-11-29 정상화 I/o 버스상의 캐쉬 일관성 비단일 메모리 엑세스 모듈을 포함하는 멀티프로세서 시스템의 프로세싱 노드 장치 및 그 제어방법
US20030041215A1 (en) * 2001-08-27 2003-02-27 George Robert T. Method and apparatus for the utilization of distributed caches
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7917646B2 (en) * 2002-12-19 2011-03-29 Intel Corporation Speculative distributed conflict resolution for a cache coherency protocol
US7111128B2 (en) * 2002-12-19 2006-09-19 Intel Corporation Hierarchical virtual model of a cache hierarchy in a multiprocessor system
US7644237B1 (en) * 2003-06-23 2010-01-05 Mips Technologies, Inc. Method and apparatus for global ordering to insure latency independent coherence
US20050262250A1 (en) * 2004-04-27 2005-11-24 Batson Brannon J Messaging protocol
US20050240734A1 (en) * 2004-04-27 2005-10-27 Batson Brannon J Cache coherence protocol
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
US8332592B2 (en) * 2004-10-08 2012-12-11 International Business Machines Corporation Graphics processor with snoop filter
US7305524B2 (en) * 2004-10-08 2007-12-04 International Business Machines Corporation Snoop filter directory mechanism in coherency shared memory system
US7577794B2 (en) * 2004-10-08 2009-08-18 International Business Machines Corporation Low latency coherency protocol for a multi-chip multiprocessor system
US7451231B2 (en) * 2005-02-10 2008-11-11 International Business Machines Corporation Data processing system, method and interconnect fabric for synchronized communication in a data processing system
US7395381B2 (en) * 2005-03-18 2008-07-01 Intel Corporation Method and an apparatus to reduce network utilization in a multiprocessor system
JP5115075B2 (ja) * 2007-07-25 2013-01-09 富士通株式会社 転送装置、転送装置を有する情報処理装置及び制御方法
JP6578992B2 (ja) * 2016-03-02 2019-09-25 富士通株式会社 制御回路、情報処理装置、および情報処理装置の制御方法
CN108123901B (zh) 2016-11-30 2020-12-29 新华三技术有限公司 一种报文传输方法和装置
US10579527B2 (en) 2018-01-17 2020-03-03 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US10387310B2 (en) 2018-01-17 2019-08-20 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US10713169B2 (en) 2018-01-17 2020-07-14 International Business Machines Corporation Remote node broadcast of requests in a multinode data processing system
US11068407B2 (en) 2018-10-26 2021-07-20 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction
US10884740B2 (en) 2018-11-08 2021-01-05 International Business Machines Corporation Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads
US11119781B2 (en) 2018-12-11 2021-09-14 International Business Machines Corporation Synchronized access to data in shared memory by protecting the load target address of a fronting load
US11106608B1 (en) 2020-06-22 2021-08-31 International Business Machines Corporation Synchronizing access to shared memory by extending protection for a target address of a store-conditional request
US11693776B2 (en) 2021-06-18 2023-07-04 International Business Machines Corporation Variable protection window extension for a target address of a store-conditional request

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535116A (en) * 1993-05-18 1996-07-09 Stanford University Flat cache-only multi-processor architectures
US5887146A (en) * 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
US5673413A (en) * 1995-12-15 1997-09-30 International Business Machines Corporation Method and apparatus for coherency reporting in a multiprocessing system
US5893144A (en) * 1995-12-22 1999-04-06 Sun Microsystems, Inc. Hybrid NUMA COMA caching system and methods for selecting between the caching modes
US5878268A (en) * 1996-07-01 1999-03-02 Sun Microsystems, Inc. Multiprocessing system configured to store coherency state within multiple subnodes of a processing node

Also Published As

Publication number Publication date
KR100324975B1 (ko) 2002-02-20
CA2271536A1 (en) 1999-12-30
JP2000112910A (ja) 2000-04-21
JP3470951B2 (ja) 2003-11-25
CA2271536C (en) 2002-07-02
US6067611A (en) 2000-05-23
KR20000005690A (ko) 2000-01-25

Similar Documents

Publication Publication Date Title
BR9903228A (pt) Sistema de processamento de dados de acesso de memória não-uniforme (numa) que armazena temporariamente potenciais transações de terceiro nó para reduzir a latência de comunicação
DE69906585D1 (de) Datenverarbeitungssystem mit nichtuniformen speicherzugriffen (numa) mit spekulativer weiterleitung einer leseanforderung an einen entfernten verarbeitungsknoten
CA2280125A1 (en) Non-uniform memory access (numa) data processing system that speculatively issues requests on a node interconnect
CA2291401A1 (en) Non-uniform memory access (numa) data processing system having shared intervention support
TWI298457B (en) System and method for cache coherency in a cache with different cache location lengths
EP0752656A3 (en) Fail-fast, fail-functional, fault-tolerant multiprocessor system
MY118269A (en) Semiconductor integrated circuit and data processing system
AU1397600A (en) Interrupt architecture for a non-uniform memory access (numa) data processing system
DE60008088D1 (de) Mehrprozessorsystem Prüfungsschaltung
BR9915265A (pt) Método e sistema para autenticar e utilizarrecursos seguros em um sistema de computador
KR960032172A (ko) 컴퓨터 시스템
KR940015805A (ko) 온-칩 (on-chip) 메모리 디바이스를 액세스하기 위해 최적화된 중앙처리 유니트 (CPU) 코어의 버스 (BUS)
PT985180E (pt) Processo para prevenir conflitos entre memorias tampao, de dados, em computacoes de fluxos de dados
BR0111204A (pt) Sistema de processamento eletrônico
CA2280172A1 (en) Non-uniform memory access (numa) data processing system that holds and reissues requests at a target processing node in response to a retry
EP1280062A3 (en) Read exclusive transaction for fast, simple invalidate
ATE433156T1 (de) Mechanismus zur umordnung von transaktionen in rechnersystemen mit snoopbasierten cachespeicherkohärenz-protokollen
BR9901209A (pt) Instruções para evitar poluição de cache.
US6347349B1 (en) System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction
EP0981092A3 (en) Non-uniform memory access (NUMA) data processing system that decreases latency by expediting rerun requests
ATE437402T1 (de) Kohärenzverwaltung über put/get-fenster
RU2216772C2 (ru) Схема обработки и схема процессора поиска
US6826619B1 (en) Method and apparatus for preventing starvation in a multi-node architecture
KR970705086A (ko) 같은 클락 사이클 동안에 캐쉬 메모리와 외부 메모리 제어기로 메모리 요청을 하는 파이프라인 마이크로프로세서(A Pipelined Microprocessor that Makes Memory Requests to a Cache Memory and an external Memory Controller During the Same Clock Cycle)
CA2081913A1 (en) Method and apparatus for managing page zero memory accesses in a multi-processor system

Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFIRO O PEDIDO DE ACORDO COM O ARTIGO 8O COMBINADO COM ARTIGO 13 DA LPI

B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: MANTIDO O INDEFERIMENTO UMA VEZ QUE NAO FOI APRESENTADO RECURSO DENTRO DO PRAZO LEGAL.