KR960032172A - 컴퓨터 시스템 - Google Patents

컴퓨터 시스템 Download PDF

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Publication number
KR960032172A
KR960032172A KR1019950067122A KR19950067122A KR960032172A KR 960032172 A KR960032172 A KR 960032172A KR 1019950067122 A KR1019950067122 A KR 1019950067122A KR 19950067122 A KR19950067122 A KR 19950067122A KR 960032172 A KR960032172 A KR 960032172A
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South Korea
Prior art keywords
endian
computer system
mechanisms
format
task
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KR1019950067122A
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English (en)
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KR100239028B1 (ko
Inventor
웨인 로엔 래리
존 실하 에드워드
Original Assignee
윌리암 티. 엘리스
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR960032172A publication Critical patent/KR960032172A/ko
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Publication of KR100239028B1 publication Critical patent/KR100239028B1/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4013—Coupling between buses with data restructuring with data re-ordering, e.g. Endian conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)

Abstract

전형적인 이중-엔디안 컴퓨터 시스템(a conventional bi-endian computer system)은 이 컴퓨터 시스템이 엔디안 모드(endian mode)를 동적으로 변환시키도록 하는 혼합-엔디안 메카니즘(mexed-dndian mechanisms)을 포함하는 향상된 시스템이다. 태스크가 대형 엔디안 포맷(big endian format) 또는 소형 엔이안 포맷(little endian format) 의 데이타를 예상하는 것에 관계없이, 혼합-엔디안 컴퓨터 시스템은 실행 태스크에 의해 예상된 유형으로 데이타를 자동적으로 포맷시킨다. 또한, 혼합-엔디안 메카니즘은 이들 메카니즘이 동일한 컴퓨터 시스템상에서 실행할 수 있도록 대형 및 소형 엔디안 인스트럭션을 포맷시킨다.

Description

컴퓨터 시스템
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 바람직한 실시예의 컴퓨터 시스템을 도시한 블럭도,
제2(a)도는 IBM PowerPC 구조에서 사용된 데이타 워드 크기를 도시한 도면,
제2(b)도는 대형 엔디안 및 소형 엔디안 데이타 포맷을 도시한 도면,
제3(a)도는 IBM PowerPC 구조의 데이타 반전 방법을 도시한 테이블,
제3(b)도는 IBM PowerPC 구조의 소형 엔디안 어드레스 변경 방법을 도시한 테이블,
제6(a)도는 본 발명의 메카니즘이 바람직한 실시예의 단계를 수행하는 방법을 도시한 논리 흐름도,
제6(b)도는 제6(a)도에 도시된 메카니즘에 의해 취해진 단계 결과의 예를 도시한 데이타 흐름도.

Claims (1)

  1. 컴퓨터 시스템(a computer system)에 있어서, 전형적인 이중-엔디안 프로세서(a conventional bi-endian processer)와; 상기 전형적인 이중-엔디안 프로세서를 기초한 태스크용 태스크(a task-for-task)에 따라, 대형 엔디안 태스크(big endian tasks)로서 실행하는 대형 엔디안 프로그램(big endian programs) 및 소형 엔디안 태스크(little endian tasks)로서 실행하는 소형 엔디안 프로그램(little endian programs)가 구비된 메모리(memory)를 포함하는 컴퓨터 시스템.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950067122A 1995-02-24 1995-12-29 컴퓨터 시스템 KR100239028B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/393,968 US5928349A (en) 1995-02-24 1995-02-24 Mixed-endian computing environment for a conventional bi-endian computer system
US8/393,968 1995-02-24
US8/393968 1995-02-24

Publications (2)

Publication Number Publication Date
KR960032172A true KR960032172A (ko) 1996-09-17
KR100239028B1 KR100239028B1 (ko) 2000-01-15

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Family Applications (1)

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KR1019950067122A KR100239028B1 (ko) 1995-02-24 1995-12-29 컴퓨터 시스템

Country Status (4)

Country Link
US (3) US5928349A (ko)
EP (1) EP0729094A1 (ko)
JP (1) JPH08314733A (ko)
KR (1) KR100239028B1 (ko)

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Also Published As

Publication number Publication date
EP0729094A1 (en) 1996-08-28
KR100239028B1 (ko) 2000-01-15
JPH08314733A (ja) 1996-11-29
US5968164A (en) 1999-10-19
US6341345B1 (en) 2002-01-22
US5928349A (en) 1999-07-27

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