KR920001332A - 고성능 프로세서의 브랜치 예상 동작 방법 및 장치 - Google Patents

고성능 프로세서의 브랜치 예상 동작 방법 및 장치 Download PDF

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KR920001332A
KR920001332A KR1019910010876A KR910010876A KR920001332A KR 920001332 A KR920001332 A KR 920001332A KR 1019910010876 A KR1019910010876 A KR 1019910010876A KR 910010876 A KR910010876 A KR 910010876A KR 920001332 A KR920001332 A KR 920001332A
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register
condition
determined
zero
processor
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KR1019910010876A
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KR100230643B1 (ko
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리챠드 엘. 사이트스
리챠드 티. 위테크
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원본미기재
디지탈 이큅먼트 코오포레이숀
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Abstract

내용 없음

Description

고성능 프로세서의 브랜치 예상 동작 방법 및 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 특징을 이용할 수 있는 CPU를 채용한 컴퓨터 시스템의 전기 블록도,
제2도는 제1도의 프로세서에 사용되는 데이타 형태에 관한 도면.

Claims (20)

  1. OP 코드 및 사인 변위를 갖는 조건부 브랜치 명령을 검출하는 단계와; 상기 변위가 포지티브이거나 네가티브인 경우 상기 브랜치 명령과 순서적으로 어드레스를 명령 추출하는 단계와; 상기 변위가 네가티브 이면 상기 변위에 의해 결정된 어드레스 명령을 추출하는 단계를 포함하는 것을 특징으로 하는 프로세서 동작 방법.
  2. 제1항에 있어서, 상기 OP코드에 의해 특정된 조건을 결정하기 위하여 상기 브랜치 명령에서 정의된 레지스터를 검사하는 단계를 추가로 포함하는 것을 특징으로 하는 프로세서 동작 방법.
  3. 제2항에 있어서, 상기 조건은 상기 레지스터가 제로와 같은 지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작 방법.
  4. 제2항에 있어서, 상기 조건은 상기 레지스터가 제로와 같지 않은지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작 방법.
  5. 제2항에 있어서, 상기 조건은 상기 레지스터가 제로 미만인지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작 방법.
  6. 제2항에 있어서, 상기 조건은 상기 레지스터가 제로 미만이거나 같은지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작 방법.
  7. 제2항에 있어서, 상기 조건은 상기 레지스터가 제로 보다 큰지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작 방법.
  8. 제2항에 있어서, 상기 조건은 상기 레지스터가 제로보다 크거나 같은지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작 방법.
  9. 제2항에 있어서, 상기 조건은 상기 레지스터의 하위 비트가 1로 설정되었는지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작 방법.
  10. 제2항에 있어서, 상기 조건은 상기 레지스터의 하위 비트가 제로인지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서 동작방법.
  11. OP코드 및 사인 변위를 갖는 조건부 브랜치 명령을 검출하는 수단과; 상기 변위가 포지티브 이거나 네가티브인 경우 상기 브랜치 명령과 순서적으로 어드레스 명령을 추출하고, 상기 변위가 네가티브인 경우 상기 변위에 의해 결정된 아드레스 명령을 추출하는 수단을 구비하는 것을 특징으로 하는 프로세서.
  12. 제11항에 있어서, 상기 OP코드에 의해 특정된 조건을 결정하기 위하여 상기 브랜치 명령에서 정의된 레지스터를 검사하기 위한 수단을 추가로 구비하는 것을 특징으로 하는 프로세서.
  13. 제12항에 있어서, 상기 조건은 상기 레지스터가 제로와 같은지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
  14. 제12항에 있어서, 상기 조건은 상기 레지스터가 제로와 같지 않은지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
  15. 제12항에 있어서, 상기 조건은 상기 레지스터가 제로 미만 인지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
  16. 제12항에 있어서, 상기 조건은 상기 레지스터가 제로 미만이거나 같은지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
  17. 제12항에 있어서, 상기 조건은 상기 레지스터가 제로보다 큰지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
  18. 제12항에 잇어서, 상기 조건은 상기 레지스터가 제로보다 크거나 같은지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
  19. 제12항에 있어서, 상기 조건은 상기 레지스터의 하위 비트가 1로 설정되었는지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
  20. 제12항에 있어서, 상기 조건은 상기 레지스터의 하위 비트가 제로인지의 여부에 따라 결정되는 것을 특징으로 하는 프로세서.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910010876A 1990-06-29 1991-06-28 고성능 프로세서의 브랜치 예상 동작 방법 및 장치 KR100230643B1 (ko)

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US54758990A 1990-06-29 1990-06-29
US547,589 1995-10-24

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KR100230643B1 KR100230643B1 (ko) 1999-11-15

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US (1) US6076158A (ko)
EP (1) EP0463973A3 (ko)
JP (1) JPH06110685A (ko)
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CA (1) CA2045790A1 (ko)
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JPH07120278B2 (ja) * 1988-07-04 1995-12-20 三菱電機株式会社 データ処理装置
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CA2045790A1 (en) 1991-12-30
JPH06110685A (ja) 1994-04-22
EP0463973A2 (en) 1992-01-02
KR100230643B1 (ko) 1999-11-15
TW222027B (ko) 1994-04-01
US6076158A (en) 2000-06-13
EP0463973A3 (en) 1993-12-01

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