KR920006845A - 파이프 라인 컴퓨터 시스템 - Google Patents

파이프 라인 컴퓨터 시스템 Download PDF

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Publication number
KR920006845A
KR920006845A KR1019910015485A KR910015485A KR920006845A KR 920006845 A KR920006845 A KR 920006845A KR 1019910015485 A KR1019910015485 A KR 1019910015485A KR 910015485 A KR910015485 A KR 910015485A KR 920006845 A KR920006845 A KR 920006845A
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South Korea
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computer system
branching
control field
condition
computer
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KR1019910015485A
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KR100242617B1 (ko
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아리 슬라벤부르크 게르리트
미쉘 라브루쎄 쟝
Original Assignee
프레데릭 얀 스미트
엔. 브이. 필립스 글로아이람펜파브리켄
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30061—Multi-way branch instructions, e.g. CASE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음

Description

파이프 라인 컴퓨터 시스템
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 조건 브랜칭 기술이 사용된 매우 긴 워드처리기와 같은 고 병렬 컴퓨터 처리기의 일반적인 블럭 다이어그램,
제6도는 본 발명에 따른 고 병렬 처리기 메모리에 대한 억세스 상태로 통로 표시 필드를 사용하는 메모리 인터페이스 제어 회로의 도시도,
제7도는 본 발명에 따른 고 병렬 처리기 메모리에 대한 억세스 상태로 통로 셋 필드를 사용하는 메모리 인터페이스 제어 회로의 도시도.

Claims (9)

  1. 컴퓨터의 각각의 머신 싸이클로 적어도 하나의 브랜칭 동작과 적어도 하나의 난-브랜칭 동작을 시작하기 위해 구성되고 상기 머신 싸이클중 적어도 하나의 브랜치 지면을 가지는 파이프 라인 컴퓨터 시스템에 있어서, 브랜치 지연동안 조건 브랜치 동작의 통로 확인 결과를 인코딩하기 위한 브랜치 제어 회로와, 그러한 동작이 실행되는 것을 확인하기 위해 브랜칭 동작에 따라 적어도 하나의 동작의 제어 필드와, 상기 브랜칭 동작에 따라 동작을 인에이블 하기 위해 통로 확인과 제어 필드를 활용하는 수단을 특징으로 하는 파이프 라인 컴퓨터 시스템
  2. 제1항에 있어서, 상기 제어 필드는 컴퓨터 시스템에 의해 각각 그리고 매동작시 나타나는 파이프 라인 컴퓨터 시스템
  3. 제1항에 있어서, 상기 제어 필드는 컴퓨터 시스템의 프로그래머-가시 상태를 실행하는 동작시만 나타나는 파이프 라인 컴퓨터 시스템.
  4. 제1항, 2항 또는 제3항에 있어서, 상기 제어 필드는 실행을 위해 하나 이상의 프로그램의 임의의 서브셋을 지정 하는 파이프 라인 컴퓨터 시스템.
  5. 디지탈 컴퓨터 처리기에 있어서, 병렬 동작에 대해 접속된 다수의 기능 유닛과, 상기 모든 기능 유닛으로 동시에 동작을 가능하게 하는 명령을 기억하기 위한 명령 레지스터 수단과, 조건 브랜칭 동작시 브랜칭을 위한 조건을 데스트하기 위한 조건 랜칭 제어 수단과, 통로 식별기를 발생하기 위해 테스팅의 결과를 인코딩하기 위한 수단과, 상기 통로 식별기와 매치되지 않아 제어 필드를 포함하는 조건 브랜칭 동작에 따라 동작 실행을 억제하는 수단을 포함하는 디지탈 컴퓨터의 처리기.
  6. 제5항에 있어서, 조건 브랜칭 동작에 따른 매 동작은 상기 통로 식별기에 대해 매치되는 필드를 포함하는 디지탈 컴퓨터 처리기.
  7. 제5항에 있어서, 상기 디지탈 컴퓨터의 프로그래머 가시상태를 실행하는 동작만 상기 통로 식별기에 대해 매치되는 필드를 포함하는 디지탈 컴퓨터 제어기.
  8. 제6항 또는 제7항에 있어서, 인코딩 수단은 하나이상의 목적 통로를 확인하는 코드로 통로 식별기를 인코딩 하는 수단을 포함하는 디지탈 컴퓨터 처리기.
  9. 제1항 내지 제4항에 있어서, 상기 브랜치 지연은 적어도 2개의 머신 싸이클인 디지탈 컴퓨터 시스템.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910015485A 1990-09-05 1991-09-05 파이프 라인 컴퓨터 시스템 KR100242617B1 (ko)

Applications Claiming Priority (2)

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US57897690A 1990-09-05 1990-09-05
US578,976 1990-09-05

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KR100242617B1 KR100242617B1 (ko) 2000-08-01

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US (1) US5450556A (ko)
EP (1) EP0474297B1 (ko)
JP (1) JP3098071B2 (ko)
KR (1) KR100242617B1 (ko)
DE (1) DE69129569T2 (ko)

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Also Published As

Publication number Publication date
KR100242617B1 (ko) 2000-08-01
EP0474297A2 (en) 1992-03-11
EP0474297A3 (en) 1993-09-01
JPH04245540A (ja) 1992-09-02
EP0474297B1 (en) 1998-06-10
DE69129569T2 (de) 1999-02-04
DE69129569D1 (de) 1998-07-16
US5450556A (en) 1995-09-12
JP3098071B2 (ja) 2000-10-10

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