DE69129569T2 - Maschine mit sehr langem Befehlswort für leistungsfähige Durchführung von Programmen mit bedingten Verzweigungen - Google Patents
Maschine mit sehr langem Befehlswort für leistungsfähige Durchführung von Programmen mit bedingten VerzweigungenInfo
- Publication number
- DE69129569T2 DE69129569T2 DE69129569T DE69129569T DE69129569T2 DE 69129569 T2 DE69129569 T2 DE 69129569T2 DE 69129569 T DE69129569 T DE 69129569T DE 69129569 T DE69129569 T DE 69129569T DE 69129569 T2 DE69129569 T2 DE 69129569T2
- Authority
- DE
- Germany
- Prior art keywords
- programs
- machine
- command word
- conditional branches
- efficient execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30061—Multi-way branch instructions, e.g. CASE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US57897690A | 1990-09-05 | 1990-09-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69129569D1 DE69129569D1 (de) | 1998-07-16 |
DE69129569T2 true DE69129569T2 (de) | 1999-02-04 |
Family
ID=24315095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69129569T Expired - Lifetime DE69129569T2 (de) | 1990-09-05 | 1991-09-02 | Maschine mit sehr langem Befehlswort für leistungsfähige Durchführung von Programmen mit bedingten Verzweigungen |
Country Status (5)
Country | Link |
---|---|
US (1) | US5450556A (de) |
EP (1) | EP0474297B1 (de) |
JP (1) | JP3098071B2 (de) |
KR (1) | KR100242617B1 (de) |
DE (1) | DE69129569T2 (de) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5832202A (en) * | 1988-12-28 | 1998-11-03 | U.S. Philips Corporation | Exception recovery in a data processing system |
US6370623B1 (en) * | 1988-12-28 | 2002-04-09 | Philips Electronics North America Corporation | Multiport register file to accommodate data of differing lengths |
JPH05233281A (ja) * | 1992-02-21 | 1993-09-10 | Toshiba Corp | 電子計算機 |
US5721854A (en) * | 1993-11-02 | 1998-02-24 | International Business Machines Corporation | Method and apparatus for dynamic conversion of computer instructions |
JP3212213B2 (ja) * | 1994-03-16 | 2001-09-25 | 株式会社日立製作所 | データ処理装置 |
JP3547482B2 (ja) * | 1994-04-15 | 2004-07-28 | 株式会社日立製作所 | 情報処理装置 |
US5581776A (en) * | 1995-02-03 | 1996-12-03 | Nokia Mobile Phones Limited | Branch control system for rom-programmed processor |
US6401190B1 (en) * | 1995-03-17 | 2002-06-04 | Hitachi, Ltd. | Parallel computing units having special registers storing large bit widths |
US5699536A (en) * | 1995-04-13 | 1997-12-16 | International Business Machines Corporation | Computer processing system employing dynamic instruction formatting |
US5815701A (en) * | 1995-06-29 | 1998-09-29 | Philips Electronics North America Corporation | Computer method and apparatus which maintains context switching speed with a large number of registers and which improves interrupt processing time |
CN1153129C (zh) * | 1995-09-01 | 2004-06-09 | 菲利浦电子北美公司 | 用于处理器定制操作的设备 |
US5774737A (en) * | 1995-10-13 | 1998-06-30 | Matsushita Electric Industrial Co., Ltd. | Variable word length very long instruction word instruction processor with word length register or instruction number register |
US5924128A (en) * | 1996-06-20 | 1999-07-13 | International Business Machines Corporation | Pseudo zero cycle address generator and fast memory access |
JP3442225B2 (ja) * | 1996-07-11 | 2003-09-02 | 株式会社日立製作所 | 演算処理装置 |
US5742804A (en) * | 1996-07-24 | 1998-04-21 | Institute For The Development Of Emerging Architectures, L.L.C. | Instruction prefetch mechanism utilizing a branch predict instruction |
US6374346B1 (en) | 1997-01-24 | 2002-04-16 | Texas Instruments Incorporated | Processor with conditional execution of every instruction |
US6055628A (en) * | 1997-01-24 | 2000-04-25 | Texas Instruments Incorporated | Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks |
US5974538A (en) * | 1997-02-21 | 1999-10-26 | Wilmot, Ii; Richard Byron | Method and apparatus for annotating operands in a computer system with source instruction identifiers |
JP3412462B2 (ja) * | 1997-07-30 | 2003-06-03 | 松下電器産業株式会社 | プロセッサ |
US7272703B2 (en) * | 1997-08-01 | 2007-09-18 | Micron Technology, Inc. | Program controlled embedded-DRAM-DSP architecture and methods |
US6170051B1 (en) | 1997-08-01 | 2001-01-02 | Micron Technology, Inc. | Apparatus and method for program level parallelism in a VLIW processor |
US6212544B1 (en) | 1997-10-23 | 2001-04-03 | International Business Machines Corporation | Altering thread priorities in a multithreaded processor |
US6697935B1 (en) | 1997-10-23 | 2004-02-24 | International Business Machines Corporation | Method and apparatus for selecting thread switch events in a multithreaded processor |
US6076157A (en) * | 1997-10-23 | 2000-06-13 | International Business Machines Corporation | Method and apparatus to force a thread switch in a multithreaded processor |
US6105051A (en) * | 1997-10-23 | 2000-08-15 | International Business Machines Corporation | Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor |
US6567839B1 (en) | 1997-10-23 | 2003-05-20 | International Business Machines Corporation | Thread switch control in a multithreaded processor system |
US5974537A (en) * | 1997-12-29 | 1999-10-26 | Philips Electronics North America Corporation | Guard bits in a VLIW instruction control routing of operations to functional units allowing two issue slots to specify the same functional unit |
US6112299A (en) * | 1997-12-31 | 2000-08-29 | International Business Machines Corporation | Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching |
US6216223B1 (en) * | 1998-01-12 | 2001-04-10 | Billions Of Operations Per Second, Inc. | Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor |
US6076154A (en) * | 1998-01-16 | 2000-06-13 | U.S. Philips Corporation | VLIW processor has different functional units operating on commands of different widths |
US6366999B1 (en) * | 1998-01-28 | 2002-04-02 | Bops, Inc. | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution |
US6314493B1 (en) | 1998-02-03 | 2001-11-06 | International Business Machines Corporation | Branch history cache |
US6178495B1 (en) * | 1998-04-30 | 2001-01-23 | International Business Machines Corporation | Processor E-unit to I-unit interface instruction modification with E-unit opcode computer logic in the unit |
US6260138B1 (en) * | 1998-07-17 | 2001-07-10 | Sun Microsystems, Inc. | Method and apparatus for branch instruction processing in a processor |
US6453407B1 (en) | 1999-02-10 | 2002-09-17 | Infineon Technologies Ag | Configurable long instruction word architecture and instruction set |
US6405300B1 (en) * | 1999-03-22 | 2002-06-11 | Sun Microsystems, Inc. | Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor |
WO2000079395A1 (en) * | 1999-06-21 | 2000-12-28 | Bops Incorporated | Methods and apparatus for establishing port priority functions in a vliw processor |
US7007156B2 (en) * | 2000-12-28 | 2006-02-28 | Intel Corporation | Multiple coprocessor architecture to process a plurality of subtasks in parallel |
WO2003034201A2 (en) * | 2001-10-12 | 2003-04-24 | Pts Corporation | Late resolving instructions |
US7200738B2 (en) | 2002-04-18 | 2007-04-03 | Micron Technology, Inc. | Reducing data hazards in pipelined processors to provide high processor utilization |
JP4283131B2 (ja) * | 2004-02-12 | 2009-06-24 | パナソニック株式会社 | プロセッサ及びコンパイル方法 |
CN1950797A (zh) * | 2004-05-13 | 2007-04-18 | 皇家飞利浦电子股份有限公司 | 多指令字处理器中反馈连接的运行时间选择 |
US8190669B1 (en) | 2004-10-20 | 2012-05-29 | Nvidia Corporation | Multipurpose arithmetic functional unit |
US8037119B1 (en) | 2006-02-21 | 2011-10-11 | Nvidia Corporation | Multipurpose functional unit with single-precision and double-precision operations |
JP2007272353A (ja) * | 2006-03-30 | 2007-10-18 | Nec Electronics Corp | プロセッサ装置及び複合条件処理方法 |
US8051123B1 (en) | 2006-12-15 | 2011-11-01 | Nvidia Corporation | Multipurpose functional unit with double-precision and filtering operations |
US8106914B2 (en) * | 2007-12-07 | 2012-01-31 | Nvidia Corporation | Fused multiply-add functional unit |
US7818552B2 (en) * | 2007-12-20 | 2010-10-19 | The United States Of America As Represented By The Secretary Of The Army | Operation, compare, branch VLIW processor |
WO2015035306A1 (en) * | 2013-09-06 | 2015-03-12 | Huawei Technologies Co., Ltd. | System and method for an asynchronous processor with token-based very long instruction word architecture |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3611306A (en) * | 1969-02-05 | 1971-10-05 | Burroughs Corp | Mechanism to control the sequencing of partially ordered instructions in a parallel data processing system |
US3781814A (en) * | 1971-10-07 | 1973-12-25 | Raytheon Co | Method and apparatus for applying source language statements to a digital computer |
US4920538A (en) * | 1985-06-28 | 1990-04-24 | International Business Machines Corporation | Method of checking the execution of microcode sequences |
US5179680A (en) * | 1987-04-20 | 1993-01-12 | Digital Equipment Corporation | Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus |
US4833599A (en) * | 1987-04-20 | 1989-05-23 | Multiflow Computer, Inc. | Hierarchical priority branch handling for parallel execution in a parallel processor |
US4943912A (en) * | 1987-10-13 | 1990-07-24 | Hitachi, Ltd. | Parallel processor system having control processor and array control apparatus for selectively activating different processors |
US5050068A (en) * | 1988-10-03 | 1991-09-17 | Duke University | Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams |
US5313551A (en) * | 1988-12-28 | 1994-05-17 | North American Philips Corporation | Multiport memory bypass under software control |
US5127092A (en) * | 1989-06-15 | 1992-06-30 | North American Philips Corp. | Apparatus and method for collective branching in a multiple instruction stream multiprocessor where any of the parallel processors is scheduled to evaluate the branching condition |
US5203002A (en) * | 1989-12-27 | 1993-04-13 | Wetzel Glen F | System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle |
CA2038264C (en) * | 1990-06-26 | 1995-06-27 | Richard James Eickemeyer | In-memory preprocessor for a scalable compound instruction set machine processor |
-
1991
- 1991-09-02 DE DE69129569T patent/DE69129569T2/de not_active Expired - Lifetime
- 1991-09-02 EP EP91202217A patent/EP0474297B1/de not_active Expired - Lifetime
- 1991-09-05 KR KR1019910015485A patent/KR100242617B1/ko not_active IP Right Cessation
- 1991-09-05 JP JP03226149A patent/JP3098071B2/ja not_active Expired - Lifetime
-
1993
- 1993-10-25 US US08/142,648 patent/US5450556A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0474297A3 (en) | 1993-09-01 |
KR920006845A (ko) | 1992-04-28 |
US5450556A (en) | 1995-09-12 |
JPH04245540A (ja) | 1992-09-02 |
DE69129569D1 (de) | 1998-07-16 |
EP0474297A2 (de) | 1992-03-11 |
EP0474297B1 (de) | 1998-06-10 |
JP3098071B2 (ja) | 2000-10-10 |
KR100242617B1 (ko) | 2000-08-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: TRIMEDIA TECHNOLOGIES, INC., SUNNYVALE, CALIF., US |
|
8328 | Change in the person/name/address of the agent |
Free format text: HOFFMANN * EITLE, 81925 MUENCHEN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NXP B.V., EINDHOVEN, NL |