BR9005193A - Sistema de verificacao de paridade de banco de memoria de computador pessoal com indicacao de erro - Google Patents

Sistema de verificacao de paridade de banco de memoria de computador pessoal com indicacao de erro

Info

Publication number
BR9005193A
BR9005193A BR909005193A BR9005193A BR9005193A BR 9005193 A BR9005193 A BR 9005193A BR 909005193 A BR909005193 A BR 909005193A BR 9005193 A BR9005193 A BR 9005193A BR 9005193 A BR9005193 A BR 9005193A
Authority
BR
Brazil
Prior art keywords
personal computer
memory bank
parity check
computer memory
parity
Prior art date
Application number
BR909005193A
Other languages
English (en)
Inventor
Louis N Cappa Jr
Jimmy G Forster
William E Price
Robert W Rupe
Kenneth Allen Uplinger
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9005193A publication Critical patent/BR9005193A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Storage Device Security (AREA)
BR909005193A 1989-10-16 1990-10-16 Sistema de verificacao de paridade de banco de memoria de computador pessoal com indicacao de erro BR9005193A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US42220489A 1989-10-16 1989-10-16

Publications (1)

Publication Number Publication Date
BR9005193A true BR9005193A (pt) 1991-09-17

Family

ID=23673830

Family Applications (1)

Application Number Title Priority Date Filing Date
BR909005193A BR9005193A (pt) 1989-10-16 1990-10-16 Sistema de verificacao de paridade de banco de memoria de computador pessoal com indicacao de erro

Country Status (11)

Country Link
EP (1) EP0423933B1 (pt)
JP (1) JPH03132829A (pt)
KR (1) KR940002273B1 (pt)
CN (1) CN1017382B (pt)
AT (1) ATE120867T1 (pt)
AU (1) AU635971B2 (pt)
BR (1) BR9005193A (pt)
CA (1) CA2021834C (pt)
DE (2) DE69018365T2 (pt)
HK (1) HK71596A (pt)
ZA (1) ZA907497B (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235602A (en) * 1991-06-11 1993-08-10 International Business Machines Corporation Synchronous/asynchronous i/o channel check and parity check detector
DE10135285B4 (de) * 2001-07-19 2005-08-04 Infineon Technologies Ag Speichereinrichtung und Verfahren zum Betreiben eines eine Speichereinrichtung enthaltenden Systems
US7275202B2 (en) * 2004-04-07 2007-09-25 International Business Machines Corporation Method, system and program product for autonomous error recovery for memory devices
US9075741B2 (en) * 2011-12-16 2015-07-07 Intel Corporation Dynamic error handling using parity and redundant rows

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619593A (en) * 1979-07-23 1981-02-24 Nippon Telegr & Teleph Corp <Ntt> Parity check processing system for memory
CA1240066A (en) * 1985-08-15 1988-08-02 John R. Ramsay Dynamic memory refresh and parity checking circuit
US4809276A (en) * 1987-02-27 1989-02-28 Hutton/Prc Technology Partners 1 Memory failure detection apparatus
DE3716594C2 (de) * 1987-05-18 1995-08-24 Siemens Ag Schaltungsanordnung für Fernmeldeanlagen, insbesondere Fernsprechvermittlungsanlagen, mit Speichereinrichtungen, in denen gespeicherte Informationsportionen auf ihre Richtigkeit überprüft werden
JPH01236331A (ja) * 1988-03-17 1989-09-21 Nec Corp エラー検出方式

Also Published As

Publication number Publication date
DE4032571C2 (pt) 1991-08-29
KR910008568A (ko) 1991-05-31
CN1017382B (zh) 1992-07-08
ZA907497B (en) 1991-06-26
ATE120867T1 (de) 1995-04-15
EP0423933A2 (en) 1991-04-24
CA2021834A1 (en) 1991-04-07
KR940002273B1 (ko) 1994-03-19
HK71596A (en) 1996-05-03
EP0423933B1 (en) 1995-04-05
EP0423933A3 (en) 1992-04-08
CA2021834C (en) 1993-12-21
DE69018365T2 (de) 1995-10-12
DE69018365D1 (de) 1995-05-11
AU635971B2 (en) 1993-04-08
CN1051095A (zh) 1991-05-01
DE4032571A1 (de) 1991-05-02
JPH03132829A (ja) 1991-06-06
AU6388890A (en) 1991-04-18

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Legal Events

Date Code Title Description
KF Request for proof of payment of annual fee
FD5 Application fees: dismissal - article 86 of industrial property law