BR8700836A - Processo de formacao de paredes laterais - Google Patents

Processo de formacao de paredes laterais

Info

Publication number
BR8700836A
BR8700836A BR8700836A BR8700836A BR8700836A BR 8700836 A BR8700836 A BR 8700836A BR 8700836 A BR8700836 A BR 8700836A BR 8700836 A BR8700836 A BR 8700836A BR 8700836 A BR8700836 A BR 8700836A
Authority
BR
Brazil
Prior art keywords
side wall
forming process
wall forming
wall
forming
Prior art date
Application number
BR8700836A
Other languages
English (en)
Inventor
Peter Leo Buchmann
Peter Vettiger
Bart Jozef Van Zeghbroeck
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8700836A publication Critical patent/BR8700836A/pt

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • G03F7/405—Treatment with inorganic or organometallic reagents after imagewise removal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/111—Narrow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/137—Resists
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer

Landscapes

  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
BR8700836A 1986-03-27 1987-02-23 Processo de formacao de paredes laterais BR8700836A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86104217A EP0238690B1 (en) 1986-03-27 1986-03-27 Process for forming sidewalls

Publications (1)

Publication Number Publication Date
BR8700836A true BR8700836A (pt) 1987-12-22

Family

ID=8195011

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8700836A BR8700836A (pt) 1986-03-27 1987-02-23 Processo de formacao de paredes laterais

Country Status (5)

Country Link
US (1) US4803181A (pt)
EP (1) EP0238690B1 (pt)
JP (1) JPH0620062B2 (pt)
BR (1) BR8700836A (pt)
DE (1) DE3682395D1 (pt)

Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5186788A (en) * 1987-07-23 1993-02-16 Matsushita Electric Industrial Co., Ltd. Fine pattern forming method
US5171718A (en) * 1987-11-27 1992-12-15 Sony Corporation Method for forming a fine pattern by using a patterned resist layer
JPH0670954B2 (ja) * 1988-01-26 1994-09-07 日本電気株式会社 半導体装置の製造方法
US5258219A (en) * 1989-01-12 1993-11-02 Seiko Epson Corporation Optimized thin film metal interconnects in integrated circuit structures of apparatus to reduce circuit operational delay
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
US5139925A (en) * 1989-10-18 1992-08-18 Massachusetts Institute Of Technology Surface barrier silylation of novolak film without photoactive additive patterned with 193 nm excimer laser
US5420067A (en) * 1990-09-28 1995-05-30 The United States Of America As Represented By The Secretary Of The Navy Method of fabricatring sub-half-micron trenches and holes
US5110760A (en) * 1990-09-28 1992-05-05 The United States Of America As Represented By The Secretary Of The Navy Method of nanometer lithography
US5202272A (en) * 1991-03-25 1993-04-13 International Business Machines Corporation Field effect transistor formed with deep-submicron gate
US5240878A (en) * 1991-04-26 1993-08-31 International Business Machines Corporation Method for forming patterned films on a substrate
US5209815A (en) * 1991-06-06 1993-05-11 International Business Machines Corporation Method for forming patterned films on a substrate
US5204280A (en) * 1992-04-09 1993-04-20 International Business Machines Corporation Process for fabricating multiple pillars inside a dram trench for increased capacitor surface
US5292689A (en) * 1992-09-04 1994-03-08 International Business Machines Corporation Method for planarizing semiconductor structure using subminimum features
KR960010056B1 (ko) * 1992-12-10 1996-07-25 삼성전자 주식회사 반도체장치 및 그 제조 방법
KR970001883B1 (ko) * 1992-12-30 1997-02-18 삼성전자 주식회사 반도체장치 및 그 제조방법
US6139483A (en) * 1993-07-27 2000-10-31 Texas Instruments Incorporated Method of forming lateral resonant tunneling devices
GB2284300B (en) * 1993-11-10 1997-11-19 Hyundai Electronics Ind Process for forming fine pattern of semiconductor device
EP0661733A2 (en) * 1993-12-21 1995-07-05 International Business Machines Corporation One dimensional silicon quantum wire devices and the method of manufacture thereof
KR970002427B1 (en) * 1994-01-14 1997-03-05 Lg Semicon Co Ltd Fine patterning method of photoresist film
US5618383A (en) * 1994-03-30 1997-04-08 Texas Instruments Incorporated Narrow lateral dimensioned microelectronic structures and method of forming the same
US5665997A (en) * 1994-03-31 1997-09-09 Texas Instruments Incorporated Grated landing area to eliminate sticking of micro-mechanical devices
JP3317582B2 (ja) * 1994-06-01 2002-08-26 菱電セミコンダクタシステムエンジニアリング株式会社 微細パターンの形成方法
US7118988B2 (en) 1994-08-15 2006-10-10 Buerger Jr Walter Richard Vertically wired integrated circuit and method of fabrication
US5667632A (en) * 1995-11-13 1997-09-16 Motorola, Inc. Method of defining a line width
US5716859A (en) * 1995-12-22 1998-02-10 The Whitaker Corporation Method of fabricating a silicon BJT
KR100524811B1 (ko) * 1996-06-27 2006-01-27 주식회사 하이닉스반도체 반도체장치의미세패턴형성방법
US5923981A (en) * 1996-12-31 1999-07-13 Intel Corporation Cascading transistor gate and method for fabricating the same
US6187694B1 (en) * 1997-11-10 2001-02-13 Intel Corporation Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
US6103596A (en) * 1998-02-19 2000-08-15 Taiwan Semiconductor Manufacturing Company Process for etching a silicon nitride hardmask mask with zero etch bias
US6100014A (en) * 1998-11-24 2000-08-08 United Microelectronics Corp. Method of forming an opening in a dielectric layer through a photoresist layer with silylated sidewall spacers
US6423475B1 (en) * 1999-03-11 2002-07-23 Advanced Micro Devices, Inc. Sidewall formation for sidewall patterning of sub 100 nm structures
US6291137B1 (en) * 1999-01-20 2001-09-18 Advanced Micro Devices, Inc. Sidewall formation for sidewall patterning of sub 100 nm structures
US5989979A (en) * 1998-12-10 1999-11-23 Chartered Semiconductor Manufacturing Ltd. Method for controlling the silicon nitride profile during patterning using a novel plasma etch process
US6124167A (en) * 1999-08-06 2000-09-26 Micron Technology, Inc. Method for forming an etch mask during the manufacture of a semiconductor device
US6107177A (en) * 1999-08-25 2000-08-22 Siemens Aktienesellschaft Silylation method for reducing critical dimension loss and resist loss
EP1228528B1 (en) * 1999-09-10 2014-08-13 Oerlikon USA Inc. Magnetic pole fabrication process and device
US6547975B1 (en) 1999-10-29 2003-04-15 Unaxis Usa Inc. Magnetic pole fabrication process and device
KR100620651B1 (ko) * 2000-06-22 2006-09-13 주식회사 하이닉스반도체 반도체 소자의 미세패턴 제조방법
US6451656B1 (en) * 2001-02-28 2002-09-17 Advanced Micro Devices, Inc. CMOS inverter configured from double gate MOSFET and method of fabricating same
US6602794B1 (en) * 2001-03-09 2003-08-05 Advanced Micro Devices, Inc. Silylation process for forming contacts
KR100374228B1 (ko) * 2001-03-28 2003-03-03 주식회사 하이닉스반도체 금속배선 형성 방법
US6605519B2 (en) * 2001-05-02 2003-08-12 Unaxis Usa, Inc. Method for thin film lift-off processes using lateral extended etching masks and device
US6733956B2 (en) * 2001-06-26 2004-05-11 Ovonyx, Inc. Method for making programmable resistance memory element
DE10142590A1 (de) 2001-08-31 2003-04-03 Infineon Technologies Ag Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße
US6862798B2 (en) 2002-01-18 2005-03-08 Hitachi Global Storage Technologies Netherlands B.V. Method of making a narrow pole tip by ion beam deposition
US20060276043A1 (en) * 2003-03-21 2006-12-07 Johnson Mark A L Method and systems for single- or multi-period edge definition lithography
US7993706B2 (en) 2004-06-08 2011-08-09 Riken Method of forming a nano-structure and the nano-structure
US7910288B2 (en) * 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
JP4804028B2 (ja) * 2005-04-25 2011-10-26 東京応化工業株式会社 ナノ構造体の製造方法
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7776744B2 (en) * 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
FR2893018B1 (fr) * 2005-11-09 2008-03-14 Commissariat Energie Atomique Procede de formation de supports presentant des motifs, tels que des masques de lithographie.
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) * 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
CN101536153B (zh) * 2006-11-06 2011-07-20 Nxp股份有限公司 制造fet栅极的方法
US8017310B2 (en) * 2007-02-02 2011-09-13 Asml Netherlands B.V. Lithographic method
KR100976647B1 (ko) * 2007-04-25 2010-08-18 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US7923373B2 (en) * 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8642474B2 (en) * 2007-07-10 2014-02-04 Advanced Micro Devices, Inc. Spacer lithography
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8012811B2 (en) * 2008-01-03 2011-09-06 International Business Machines Corporation Methods of forming features in integrated circuits
US8168542B2 (en) * 2008-01-03 2012-05-01 International Business Machines Corporation Methods of forming tubular objects
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8329385B2 (en) * 2008-06-10 2012-12-11 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US20100308409A1 (en) * 2009-06-08 2010-12-09 Globalfoundries Inc. Finfet structures with fins having stress-inducing caps and methods for fabricating the same
JP5782279B2 (ja) * 2011-01-20 2015-09-24 株式会社Ｓｃｒｅｅｎホールディングス 基板処理方法および基板処理装置
JP2022115656A (ja) 2021-01-28 2022-08-09 キオクシア株式会社 半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5656636A (en) * 1979-10-13 1981-05-18 Mitsubishi Electric Corp Processing method of fine pattern
US4377437A (en) * 1981-05-22 1983-03-22 Bell Telephone Laboratories, Incorporated Device lithography by selective ion implantation
US4389482A (en) * 1981-12-14 1983-06-21 International Business Machines Corporation Process for forming photoresists with strong resistance to reactive ion etching and high sensitivity to mid- and deep UV-light
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4445267A (en) * 1981-12-30 1984-05-01 International Business Machines Corporation MOSFET Structure and process to form micrometer long source/drain spacing
GB2121198A (en) * 1982-05-26 1983-12-14 Philips Electronic Associated Plasma-etch resistant mask formation
DE3242113A1 (de) * 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper
CA1248402A (en) * 1983-09-16 1989-01-10 Larry E. Stillwagon Method of making articles using gas functionalized plasma developed layer
US4552833A (en) * 1984-05-14 1985-11-12 International Business Machines Corporation Radiation sensitive and oxygen plasma developable resist
US4601778A (en) * 1985-02-25 1986-07-22 Motorola, Inc. Maskless etching of polysilicon
US4613398A (en) * 1985-06-06 1986-09-23 International Business Machines Corporation Formation of etch-resistant resists through preferential permeation
US4657845A (en) * 1986-01-14 1987-04-14 International Business Machines Corporation Positive tone oxygen plasma developable photoresist

Also Published As

Publication number Publication date
JPH0620062B2 (ja) 1994-03-16
US4803181A (en) 1989-02-07
EP0238690B1 (en) 1991-11-06
EP0238690A1 (en) 1987-09-30
DE3682395D1 (de) 1991-12-12
JPS62232127A (ja) 1987-10-12

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Legal Events

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B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 23/02/2002