BR8104309A - Processo para fabricar um dispositivo semicondutor apassivado a vidro e dispositivo semicondutor - Google Patents

Processo para fabricar um dispositivo semicondutor apassivado a vidro e dispositivo semicondutor

Info

Publication number
BR8104309A
BR8104309A BR8104309A BR8104309A BR8104309A BR 8104309 A BR8104309 A BR 8104309A BR 8104309 A BR8104309 A BR 8104309A BR 8104309 A BR8104309 A BR 8104309A BR 8104309 A BR8104309 A BR 8104309A
Authority
BR
Brazil
Prior art keywords
semiconductor device
apassivated
glass
manufacturing
semiconductor
Prior art date
Application number
BR8104309A
Other languages
English (en)
Inventor
John A Ostop
Joseph E Johnson
Original Assignee
Westinghouse Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westinghouse Electric Corp filed Critical Westinghouse Electric Corp
Publication of BR8104309A publication Critical patent/BR8104309A/pt

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3178Coating or filling in grooves made in the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10157Shape being other than a cuboid at the active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)
BR8104309A 1980-07-10 1981-07-07 Processo para fabricar um dispositivo semicondutor apassivado a vidro e dispositivo semicondutor BR8104309A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16881880A 1980-07-10 1980-07-10

Publications (1)

Publication Number Publication Date
BR8104309A true BR8104309A (pt) 1982-03-23

Family

ID=22613059

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8104309A BR8104309A (pt) 1980-07-10 1981-07-07 Processo para fabricar um dispositivo semicondutor apassivado a vidro e dispositivo semicondutor

Country Status (5)

Country Link
EP (1) EP0044048A1 (pt)
JP (1) JPS5748240A (pt)
BR (1) BR8104309A (pt)
CA (1) CA1177975A (pt)
IN (1) IN154896B (pt)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR8203630A (pt) * 1981-06-29 1983-06-14 Westinghouse Electric Corp Dispositivo semicondutor processo de preparacao de uma pluralidade de dispositivos semicondutores apassivados com vidro
DE3247938A1 (de) * 1982-12-24 1984-07-05 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Halbleiterbauelement hoher sperrspannungsbelastbarkeit
US5739048A (en) * 1994-05-23 1998-04-14 International Business Machines Corporation Method for forming rows of partially separated thin film elements
CN102263167B (zh) * 2011-08-15 2013-04-17 英利能源(中国)有限公司 单晶硅太阳电池的边沿钝化方法、单晶硅太阳电池及其制备方法和光伏组件
JP6190740B2 (ja) * 2014-03-11 2017-08-30 新電元工業株式会社 半導体装置及び半導体装置の製造方法
DE102016124670B4 (de) * 2016-12-16 2020-01-23 Semikron Elektronik Gmbh & Co. Kg Thyristor mit einem Halbleiterkörper
JP7456220B2 (ja) * 2020-03-19 2024-03-27 Tdk株式会社 ショットキーバリアダイオード
CN113517205A (zh) * 2020-04-27 2021-10-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11699663B2 (en) 2020-04-27 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme design for wafer singulation
CN113299567B (zh) * 2021-05-24 2024-02-02 捷捷半导体有限公司 一种钝化层制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3632434A (en) * 1969-01-21 1972-01-04 Jerald L Hutson Process for glass passivating silicon semiconductor junctions
US3628107A (en) * 1969-05-05 1971-12-14 Gen Electric Passivated semiconductor device with peripheral protective junction
US3608186A (en) * 1969-10-30 1971-09-28 Jearld L Hutson Semiconductor device manufacture with junction passivation
US3755720A (en) * 1972-09-25 1973-08-28 Rca Corp Glass encapsulated semiconductor device
DE2739762C2 (de) * 1977-09-03 1982-12-02 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Verfahren zur Passivierung von Halbleiterkörpern
US4235645A (en) * 1978-12-15 1980-11-25 Westinghouse Electric Corp. Process for forming glass-sealed multichip semiconductor devices

Also Published As

Publication number Publication date
CA1177975A (en) 1984-11-13
EP0044048A1 (en) 1982-01-20
IN154896B (pt) 1984-12-22
JPS5748240A (en) 1982-03-19

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