BR112016003865A2 - Treinamento de leitura de um controlador de memória - Google Patents

Treinamento de leitura de um controlador de memória

Info

Publication number
BR112016003865A2
BR112016003865A2 BR112016003865A BR112016003865A BR112016003865A2 BR 112016003865 A2 BR112016003865 A2 BR 112016003865A2 BR 112016003865 A BR112016003865 A BR 112016003865A BR 112016003865 A BR112016003865 A BR 112016003865A BR 112016003865 A2 BR112016003865 A2 BR 112016003865A2
Authority
BR
Brazil
Prior art keywords
memory controller
reading training
controller reading
training
memory
Prior art date
Application number
BR112016003865A
Other languages
English (en)
Inventor
Tonia G Morris
Jonathan C Jasper
Arnaud J Forestier
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112016003865A2 publication Critical patent/BR112016003865A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0632—Configuration or reconfiguration of storage systems by initialisation or re-initialisation of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Databases & Information Systems (AREA)
  • Memory System (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Error Detection And Correction (AREA)
BR112016003865A 2013-09-27 2014-07-29 Treinamento de leitura de um controlador de memória BR112016003865A2 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/040,548 US9021154B2 (en) 2013-09-27 2013-09-27 Read training a memory controller

Publications (1)

Publication Number Publication Date
BR112016003865A2 true BR112016003865A2 (pt) 2017-08-01

Family

ID=52741301

Family Applications (3)

Application Number Title Priority Date Filing Date
BR112016003865A BR112016003865A2 (pt) 2013-09-27 2014-07-29 Treinamento de leitura de um controlador de memória
BR122017013543-0A BR122017013543B1 (pt) 2013-09-27 2014-07-29 Dispositivo de circuito integrado e sistema para treinamento de leitura de um controlador de memória
BR122017013533-3A BR122017013533B1 (pt) 2013-09-27 2014-07-29 Dispositivo de circuito integrado e sistema para treinamento de leitura de um controlador de memória

Family Applications After (2)

Application Number Title Priority Date Filing Date
BR122017013543-0A BR122017013543B1 (pt) 2013-09-27 2014-07-29 Dispositivo de circuito integrado e sistema para treinamento de leitura de um controlador de memória
BR122017013533-3A BR122017013533B1 (pt) 2013-09-27 2014-07-29 Dispositivo de circuito integrado e sistema para treinamento de leitura de um controlador de memória

Country Status (8)

Country Link
US (6) US9021154B2 (pt)
EP (1) EP3049946B1 (pt)
JP (4) JP6084756B2 (pt)
KR (3) KR102058019B1 (pt)
CN (2) CN112069110B (pt)
BR (3) BR112016003865A2 (pt)
RU (1) RU2643664C2 (pt)
WO (1) WO2015047532A1 (pt)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9021154B2 (en) 2013-09-27 2015-04-28 Intel Corporation Read training a memory controller
US10074417B2 (en) * 2014-11-20 2018-09-11 Rambus Inc. Memory systems and methods for improved power management
US10025747B2 (en) * 2015-05-07 2018-07-17 Samsung Electronics Co., Ltd. I/O channel scrambling/ECC disassociated communication protocol
US9921763B1 (en) * 2015-06-25 2018-03-20 Crossbar, Inc. Multi-bank non-volatile memory apparatus with high-speed bus
US10222989B1 (en) 2015-06-25 2019-03-05 Crossbar, Inc. Multiple-bank memory device with status feedback for subsets of memory banks
US10141034B1 (en) 2015-06-25 2018-11-27 Crossbar, Inc. Memory apparatus with non-volatile two-terminal memory and expanded, high-speed bus
US9558850B1 (en) 2015-12-01 2017-01-31 International Business Machines Corporation Efficient calibration of a data eye for memory devices
US9620184B1 (en) 2015-12-16 2017-04-11 International Business Machines Corporation Efficient calibration of memory devices
KR102536657B1 (ko) * 2016-07-12 2023-05-30 에스케이하이닉스 주식회사 반도체 장치 및 반도체 시스템
US10034407B2 (en) * 2016-07-22 2018-07-24 Intel Corporation Storage sled for a data center
US10552252B2 (en) * 2016-08-29 2020-02-04 Seagate Technology Llc Patterned bit in error measurement apparatus and method
US10067689B1 (en) * 2016-08-29 2018-09-04 Cadence Design Systems, Inc. Method and apparatus for high bandwidth memory read and write data path training
US10148416B2 (en) 2016-09-02 2018-12-04 Intel Corporation Signal phase optimization in memory interface training
US10262751B2 (en) * 2016-09-29 2019-04-16 Intel Corporation Multi-dimensional optimization of electrical parameters for memory training
KR20180049338A (ko) * 2016-10-31 2018-05-11 삼성전자주식회사 저장 장치 및 그것의 동작 방법
US10416912B2 (en) 2016-11-03 2019-09-17 Intel Corporation Efficiently training memory device chip select control
KR102687267B1 (ko) * 2016-12-15 2024-07-22 에스케이하이닉스 주식회사 반도체 장치, 반도체 시스템 및 트레이닝 방법
KR102532173B1 (ko) 2017-06-23 2023-05-16 후아웨이 테크놀러지 컴퍼니 리미티드 메모리 액세스 기술 및 컴퓨터 시스템
KR102353027B1 (ko) * 2017-07-03 2022-01-20 삼성전자주식회사 스토리지 장치의 데이터 트레이닝 방법
US20190095308A1 (en) 2017-09-26 2019-03-28 Intel Corporation Registering clock driver controlled decision feedback equalizer training process
US10810141B2 (en) * 2017-09-29 2020-10-20 Intel Corporation Memory control management of a processor
US11074151B2 (en) 2018-03-30 2021-07-27 Intel Corporation Processor having embedded non-volatile random access memory to support processor monitoring software
US10691466B2 (en) * 2018-04-02 2020-06-23 Intel Corporation Booting a computing system using embedded non-volatile memory
JP2019215662A (ja) * 2018-06-12 2019-12-19 株式会社日立製作所 不揮発性メモリデバイス、及びインターフェース設定方法
JP2020046918A (ja) 2018-09-19 2020-03-26 キオクシア株式会社 記憶装置及び制御方法
KR102685470B1 (ko) * 2018-12-24 2024-07-17 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 장치 및 반도체 시스템
KR102648186B1 (ko) * 2018-12-24 2024-03-18 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 시스템
CN110210018B (zh) * 2019-05-14 2023-07-11 北京百度网讯科技有限公司 挂号科室的匹配方法和装置
CN113728385A (zh) 2019-05-24 2021-11-30 英特尔公司 针对存储器设备的芯片选择信号读取操作的训练
CN112764667B (zh) * 2019-10-21 2024-09-06 伊姆西Ip控股有限责任公司 用于存储管理的方法、设备、存储系统和计算机程序产品
TWI693796B (zh) * 2019-11-08 2020-05-11 群聯電子股份有限公司 訊號產生電路、記憶體儲存裝置及訊號產生方法
US11126585B1 (en) 2020-03-09 2021-09-21 Western Digital Technologies, Inc. Data storage device with improved interface transmitter training
US11288225B2 (en) 2020-04-14 2022-03-29 Western Digital Technologies, Inc. Adapting transmitter training behavior based upon assumed identity of training partner
KR20210136203A (ko) * 2020-05-06 2021-11-17 삼성전자주식회사 저장 장치 및 그것의 리트레이닝 방법
US11190331B1 (en) * 2020-12-16 2021-11-30 Cadence Design Systems, Inc. Data alignment in physical layer device
CN116052742B (zh) * 2022-07-13 2024-07-02 成都海光集成电路设计有限公司 数据处理方法、装置、存储控制器、设备及介质

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
KR100233122B1 (ko) 1992-03-25 1999-12-01 윤종용 모뎀 운용 테스트 회로
US6266379B1 (en) * 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
JP3922765B2 (ja) 1997-07-22 2007-05-30 富士通株式会社 半導体装置システム及び半導体装置
JPH11139869A (ja) 1997-11-10 1999-05-25 Murata Mfg Co Ltd 半導体セラミックおよびその製造方法
JP2002082830A (ja) 2000-02-14 2002-03-22 Mitsubishi Electric Corp インターフェイス回路
WO2001084724A2 (en) 2000-04-28 2001-11-08 Broadcom Corporation Methods and systems for adaptive receiver equalization
US6651148B2 (en) * 2000-05-23 2003-11-18 Canon Kabushiki Kaisha High-speed memory controller for pipelining memory read transactions
US6658523B2 (en) 2001-03-13 2003-12-02 Micron Technology, Inc. System latency levelization for read data
US7437624B2 (en) 2002-09-30 2008-10-14 Lecroy Corporation Method and apparatus for analyzing serial data streams
US7167946B2 (en) 2003-09-30 2007-01-23 Intel Corporation Method and apparatus for implicit DRAM precharge
US6958634B2 (en) 2003-12-24 2005-10-25 Intel Corporation Programmable direct interpolating delay locked loop
US7403584B2 (en) 2003-12-31 2008-07-22 Intel Corporation Programmable phase interpolator adjustment for ideal data eye sampling
US7107424B1 (en) * 2004-03-25 2006-09-12 Emc Corporation Memory read strobe pulse optimization training system
KR100594294B1 (ko) * 2004-09-21 2006-06-30 삼성전자주식회사 메모리 장치 및 데이터 트레이닝 방법
KR100618870B1 (ko) * 2004-10-23 2006-08-31 삼성전자주식회사 데이터 트레이닝 방법
JP2006260071A (ja) * 2005-03-16 2006-09-28 Oki Data Corp メモリ制御装置および情報処理装置
KR100703976B1 (ko) * 2005-08-29 2007-04-06 삼성전자주식회사 동기식 메모리 장치
US7607031B2 (en) * 2006-03-28 2009-10-20 Advanced Micro Devices, Inc. Power management in a communication link
US7904639B2 (en) 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
US7983368B2 (en) * 2006-12-11 2011-07-19 International Business Machines Corporation Systems and arrangements for clock and data recovery in communications
US7814401B2 (en) 2006-12-21 2010-10-12 Ramot At Tel Aviv University Ltd. Soft decoding of hard and soft bits read from a flash memory
US7886174B2 (en) 2007-06-27 2011-02-08 Intel Corporation Memory link training
US8341450B2 (en) * 2007-07-23 2012-12-25 Rambus Inc. Continuous timing calibrated memory interface
US7913033B2 (en) 2007-10-09 2011-03-22 Micron Technology, Inc. Non-volatile memory device having assignable network identification
US8793525B2 (en) * 2007-10-22 2014-07-29 Rambus Inc. Low-power source-synchronous signaling
JP2012515376A (ja) * 2009-01-12 2012-07-05 ラムバス・インコーポレーテッド クロック転送低電力シグナリングシステム
US7978538B2 (en) * 2009-01-29 2011-07-12 International Business Machines Corporation Setting memory device termination in a memory device and memory controller interface in a communication bus
US8037375B2 (en) * 2009-06-30 2011-10-11 Intel Corporation Fast data eye retraining for a memory
US8578086B2 (en) 2009-09-25 2013-11-05 Intel Corporation Memory link initialization
US8681571B2 (en) * 2010-06-15 2014-03-25 International Business Machines Corporation Training a memory controller and a memory device using multiple read and write operations
US8533538B2 (en) * 2010-06-28 2013-09-10 Intel Corporation Method and apparatus for training a memory signal via an error signal of a memory
KR20120011491A (ko) 2010-07-29 2012-02-08 주식회사 하이닉스반도체 반도체 시스템 및 그 데이터 트래이닝 방법
US20120066471A1 (en) 2010-09-14 2012-03-15 Advanced Micro Devices, Inc. Allocation of memory buffers based on preferred memory performance
US8631256B2 (en) * 2010-12-22 2014-01-14 Via Technologies, Inc. Distributed management of a shared power source to a multi-core microprocessor
JP5792384B2 (ja) * 2011-07-01 2015-10-14 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ シリアル通信システムにおけるスタンバイ電力低減のためのシステムおよび方法
US8954408B2 (en) 2011-07-28 2015-02-10 International Business Machines Corporation Allowing writes to complete without obtaining a write lock to a file
US9021154B2 (en) 2013-09-27 2015-04-28 Intel Corporation Read training a memory controller

Also Published As

Publication number Publication date
JP2017107584A (ja) 2017-06-15
BR122017013533B1 (pt) 2023-03-07
US20150113234A1 (en) 2015-04-23
US20170286330A1 (en) 2017-10-05
KR102058019B1 (ko) 2019-12-20
KR20160034961A (ko) 2016-03-30
CN105723351A (zh) 2016-06-29
CN112069110A (zh) 2020-12-11
EP3049946B1 (en) 2021-06-23
KR101855512B1 (ko) 2018-06-25
US9058111B2 (en) 2015-06-16
JP6084756B2 (ja) 2017-02-22
KR102058018B1 (ko) 2019-12-20
KR20180050765A (ko) 2018-05-15
BR122017013543B1 (pt) 2023-03-07
EP3049946A1 (en) 2016-08-03
EP3049946A4 (en) 2017-04-26
US10482041B2 (en) 2019-11-19
US20150095565A1 (en) 2015-04-02
JP2016534472A (ja) 2016-11-04
US20150113215A1 (en) 2015-04-23
RU2643664C2 (ru) 2018-02-02
US10331585B2 (en) 2019-06-25
US9766817B2 (en) 2017-09-19
CN112069110B (zh) 2024-09-13
JP6327762B2 (ja) 2018-05-23
JP6327763B2 (ja) 2018-05-23
US9021154B2 (en) 2015-04-28
JP2017097907A (ja) 2017-06-01
WO2015047532A1 (en) 2015-04-02
US20170031846A1 (en) 2017-02-02
US20150113235A1 (en) 2015-04-23
JP6327764B2 (ja) 2018-05-23
KR20180049244A (ko) 2018-05-10
US9495103B2 (en) 2016-11-15
RU2016107022A (ru) 2017-08-31
CN105723351B (zh) 2020-08-18
JP2017097908A (ja) 2017-06-01

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B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements