AU9798698A - Method and apparatus for fail-safe resynchronization with minimum latency - Google Patents

Method and apparatus for fail-safe resynchronization with minimum latency

Info

Publication number
AU9798698A
AU9798698A AU97986/98A AU9798698A AU9798698A AU 9798698 A AU9798698 A AU 9798698A AU 97986/98 A AU97986/98 A AU 97986/98A AU 9798698 A AU9798698 A AU 9798698A AU 9798698 A AU9798698 A AU 9798698A
Authority
AU
Australia
Prior art keywords
bus
clocks
circuit
latency
resynchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU97986/98A
Other languages
English (en)
Inventor
Abhijit M. Abhyankar
Richard M Barth
Andy Peng-Pui Chan
Michael Tak-Kei Ching
Paul G. Davis
William F. Stonecypher
Jared Levan Zerbe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of AU9798698A publication Critical patent/AU9798698A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045—Correction by a latch cascade
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)
  • Retry When Errors Occur (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
AU97986/98A 1997-10-10 1998-10-09 Method and apparatus for fail-safe resynchronization with minimum latency Abandoned AU9798698A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US6150597P 1997-10-10 1997-10-10
US60061505 1997-10-10
PCT/US1998/021448 WO1999019806A1 (en) 1997-10-10 1998-10-09 Method and apparatus for fail-safe resynchronization with minimum latency

Publications (1)

Publication Number Publication Date
AU9798698A true AU9798698A (en) 1999-05-03

Family

ID=22036219

Family Applications (1)

Application Number Title Priority Date Filing Date
AU97986/98A Abandoned AU9798698A (en) 1997-10-10 1998-10-09 Method and apparatus for fail-safe resynchronization with minimum latency

Country Status (8)

Country Link
US (3) US6473439B1 (https=)
EP (1) EP1031093B1 (https=)
JP (1) JP4484359B2 (https=)
KR (1) KR100603687B1 (https=)
AT (1) ATE232317T1 (https=)
AU (1) AU9798698A (https=)
DE (1) DE69811262T2 (https=)
WO (1) WO1999019806A1 (https=)

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Also Published As

Publication number Publication date
ATE232317T1 (de) 2003-02-15
DE69811262D1 (de) 2003-03-13
KR100603687B1 (ko) 2006-07-20
DE69811262T2 (de) 2003-11-27
EP1031093A1 (en) 2000-08-30
WO1999019806A1 (en) 1999-04-22
US6949958B2 (en) 2005-09-27
JP4484359B2 (ja) 2010-06-16
KR20010031036A (ko) 2001-04-16
JP2001520417A (ja) 2001-10-30
US20060022724A1 (en) 2006-02-02
US6473439B1 (en) 2002-10-29
US20030053489A1 (en) 2003-03-20
US7288973B2 (en) 2007-10-30
EP1031093B1 (en) 2003-02-05

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