AU721764B2 - High performance universal multi-port internally cached dynamic random access memory system, architecture and method - Google Patents

High performance universal multi-port internally cached dynamic random access memory system, architecture and method Download PDF

Info

Publication number
AU721764B2
AU721764B2 AU65295/96A AU6529596A AU721764B2 AU 721764 B2 AU721764 B2 AU 721764B2 AU 65295/96 A AU65295/96 A AU 65295/96A AU 6529596 A AU6529596 A AU 6529596A AU 721764 B2 AU721764 B2 AU 721764B2
Authority
AU
Australia
Prior art keywords
data
dram
serial
buffers
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU65295/96A
Other languages
English (en)
Other versions
AU6529596A (en
Inventor
Mukesh Chatter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU6529596A publication Critical patent/AU6529596A/en
Application granted granted Critical
Publication of AU721764B2 publication Critical patent/AU721764B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Static Random-Access Memory (AREA)
  • Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
AU65295/96A 1995-12-29 1996-08-12 High performance universal multi-port internally cached dynamic random access memory system, architecture and method Ceased AU721764B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/581,467 US5799209A (en) 1995-12-29 1995-12-29 Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US08/581467 1995-12-29
PCT/IB1996/000794 WO1997024725A1 (en) 1995-12-29 1996-08-12 High performance universal multi-port internally cached dynamic random access memory system, architecture and method

Publications (2)

Publication Number Publication Date
AU6529596A AU6529596A (en) 1997-07-28
AU721764B2 true AU721764B2 (en) 2000-07-13

Family

ID=24325313

Family Applications (1)

Application Number Title Priority Date Filing Date
AU65295/96A Ceased AU721764B2 (en) 1995-12-29 1996-08-12 High performance universal multi-port internally cached dynamic random access memory system, architecture and method

Country Status (15)

Country Link
US (2) US5799209A (zh)
EP (1) EP0870303B1 (zh)
JP (1) JP3699126B2 (zh)
KR (1) KR100328603B1 (zh)
CN (1) CN1120495C (zh)
AT (1) ATE197101T1 (zh)
AU (1) AU721764B2 (zh)
CA (1) CA2241841C (zh)
DE (1) DE69610714T2 (zh)
DK (1) DK0870303T3 (zh)
GR (1) GR3035261T3 (zh)
HK (1) HK1018342A1 (zh)
IL (1) IL125135A (zh)
TW (1) TW318222B (zh)
WO (1) WO1997024725A1 (zh)

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118776A (en) * 1997-02-18 2000-09-12 Vixel Corporation Methods and apparatus for fiber channel interconnection of private loop devices
JPH10283088A (ja) * 1997-04-02 1998-10-23 Oki Electric Ind Co Ltd シリアル通信回路
AU744329B2 (en) * 1997-04-30 2002-02-21 Canon Kabushiki Kaisha Data normalization circuit and method
JP3733699B2 (ja) * 1997-06-20 2006-01-11 ソニー株式会社 シリアルインタフェース回路
US5918074A (en) * 1997-07-25 1999-06-29 Neonet Llc System architecture for and method of dual path data processing and management of packets and/or cells and the like
US6212597B1 (en) * 1997-07-28 2001-04-03 Neonet Lllc Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like
US6108758A (en) * 1997-08-29 2000-08-22 Intel Corporation Multiple masters in a memory control system
US6067595A (en) * 1997-09-23 2000-05-23 Icore Technologies, Inc. Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
KR100261218B1 (ko) * 1997-12-08 2000-07-01 윤종용 반도체 메모리 장치의 핀 어사인먼트 방법 및 패킷 단위의 신호를 입력으로 하는 반도체 메모리장치
US6622224B1 (en) * 1997-12-29 2003-09-16 Micron Technology, Inc. Internal buffered bus for a drum
US6085290A (en) * 1998-03-10 2000-07-04 Nexabit Networks, Llc Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM)
US6138219A (en) * 1998-03-27 2000-10-24 Nexabit Networks Llc Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access
US6003121A (en) * 1998-05-18 1999-12-14 Intel Corporation Single and multiple channel memory detection and sizing
US6112267A (en) * 1998-05-28 2000-08-29 Digital Equipment Corporation Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels
FR2779843A1 (fr) * 1998-06-16 1999-12-17 Busless Computers Composant memoire multiport serie et application a un ordinateur
US6122680A (en) * 1998-06-18 2000-09-19 Lsi Logic Corporation Multiple channel data communication buffer with separate single port transmit and receive memories having a unique channel for each communication port and with fixed arbitration
US6237130B1 (en) * 1998-10-29 2001-05-22 Nexabit Networks, Inc. Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like
US5991163A (en) * 1998-11-12 1999-11-23 Nexabit Networks, Inc. Electronic circuit board assembly and method of closely stacking boards and cooling the same
US6272567B1 (en) * 1998-11-24 2001-08-07 Nexabit Networks, Inc. System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed
US6389494B1 (en) * 1998-12-30 2002-05-14 Emc Corporation System for interfacing a data storage system to a host utilizing a plurality of busses for carrying end-user data and a separate bus for carrying interface state data
US7073020B1 (en) 1999-01-04 2006-07-04 Emc Corporation Method for message transfer in computer storage system
US7117275B1 (en) 1999-01-04 2006-10-03 Emc Corporation Data storage system having separate data transfer section and message network
US6467018B1 (en) * 1999-01-04 2002-10-15 International Business Machines Corporation Method and apparatus for addressing individual banks of DRAMs on a memory card
US6345345B1 (en) * 1999-01-26 2002-02-05 Advanced Micro Devices, Inc. Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers
CA2367878A1 (en) * 1999-03-26 2000-10-05 Richard F. Conlin Ampic dram system
US6412032B1 (en) * 1999-09-30 2002-06-25 Rockwell Automation Technologies, Inc. Interface for industrial controller network card
DE19951046A1 (de) * 1999-10-22 2001-04-26 Siemens Ag Speicherbaustein für ein Mehrprozessorsystem und Mehrprozessorsystem
US6628662B1 (en) 1999-11-29 2003-09-30 International Business Machines Corporation Method and system for multilevel arbitration in a non-blocking crossbar switch
US7010575B1 (en) 2000-03-31 2006-03-07 Emc Corporation Data storage system having separate data transfer section and message network having bus arbitration
US7007194B1 (en) 2000-06-29 2006-02-28 Emc Corporation Data storage system having point-to-point configuration
US6779071B1 (en) 2000-04-28 2004-08-17 Emc Corporation Data storage system having separate data transfer section and message network with status register
US6651130B1 (en) 2000-04-28 2003-11-18 Emc Corporation Data storage system having separate data transfer section and message network with bus arbitration
KR20010106079A (ko) * 2000-05-19 2001-11-29 강 크리스토퍼 파이프라인된 스위치 구성 디바이스
US6349058B1 (en) * 2001-02-16 2002-02-19 Microchip Technology Incorporated Electronic circuit and method for storing configuration and calibration information in a non-volatile memory array
US6924538B2 (en) 2001-07-25 2005-08-02 Nantero, Inc. Devices having vertically-disposed nanofabric articles and methods of making the same
US6911682B2 (en) 2001-12-28 2005-06-28 Nantero, Inc. Electromechanical three-trace junction devices
US7259410B2 (en) 2001-07-25 2007-08-21 Nantero, Inc. Devices having horizontally-disposed nanofabric articles and methods of making the same
US6574130B2 (en) 2001-07-25 2003-06-03 Nantero, Inc. Hybrid circuit having nanotube electromechanical memory
US6706402B2 (en) 2001-07-25 2004-03-16 Nantero, Inc. Nanotube films and articles
US7566478B2 (en) 2001-07-25 2009-07-28 Nantero, Inc. Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles
US6919592B2 (en) 2001-07-25 2005-07-19 Nantero, Inc. Electromechanical memory array using nanotube ribbons and method for making same
US6835591B2 (en) 2001-07-25 2004-12-28 Nantero, Inc. Methods of nanotube films and articles
US6643165B2 (en) 2001-07-25 2003-11-04 Nantero, Inc. Electromechanical memory having cell selection circuitry constructed with nanotube technology
US6988161B2 (en) * 2001-12-20 2006-01-17 Intel Corporation Multiple port allocation and configurations for different port operation modes on a host
US6784028B2 (en) 2001-12-28 2004-08-31 Nantero, Inc. Methods of making electromechanical three-trace junction devices
US7176505B2 (en) 2001-12-28 2007-02-13 Nantero, Inc. Electromechanical three-trace junction devices
US7335395B2 (en) 2002-04-23 2008-02-26 Nantero, Inc. Methods of using pre-formed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles
DE10253918A1 (de) * 2002-11-19 2004-06-17 Infineon Technologies Ag Speichersystem, insbesondere für Netzwerk-Broadcasting-Anwendungen wie Video-/Audio-Anwendungen, sowie Verfahren zum Betrieb eines Speichersystems
US7099983B2 (en) * 2002-11-25 2006-08-29 Lsi Logic Corporation Multi-core communications module, data communications system incorporating a multi-core communications module, and data communications process
US7560136B2 (en) 2003-01-13 2009-07-14 Nantero, Inc. Methods of using thin metal layers to make carbon nanotube films, layers, fabrics, ribbons, elements and articles
US7571287B2 (en) * 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
KR100518572B1 (ko) * 2003-05-15 2005-10-04 삼성전자주식회사 직렬 멀티 포트 통신 방법, 이에 적합한 장치, 이 장치를제어하는 방법, 그리고 이 제어 방법에 적합한 기록 매체
JP2004355351A (ja) * 2003-05-29 2004-12-16 Hitachi Ltd サーバ装置
CN100390755C (zh) * 2003-10-14 2008-05-28 中国科学院计算技术研究所 含有显式高速缓冲存储器的计算机微体系结构
US7587521B2 (en) * 2005-06-23 2009-09-08 Intel Corporation Mechanism for assembling memory access requests while speculatively returning data
US8332598B2 (en) 2005-06-23 2012-12-11 Intel Corporation Memory micro-tiling request reordering
US7765366B2 (en) * 2005-06-23 2010-07-27 Intel Corporation Memory micro-tiling
US8253751B2 (en) * 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US7558941B2 (en) * 2005-06-30 2009-07-07 Intel Corporation Automatic detection of micro-tile enabled memory
JP2007334564A (ja) * 2006-06-14 2007-12-27 Matsushita Electric Ind Co Ltd ユニファイドメモリシステム
JP5018074B2 (ja) * 2006-12-22 2012-09-05 富士通セミコンダクター株式会社 メモリ装置,メモリコントローラ及びメモリシステム
EP2104089A4 (en) 2007-01-12 2010-01-13 Panasonic Corp PLASMA DISPLAY PANEL AND ITS EXCITATION METHOD
CN101216751B (zh) * 2008-01-21 2010-07-14 戴葵 基于分布存储结构的具有数据处理能力的动态随机存储器装置
JP5599969B2 (ja) 2008-03-19 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル マルチポートメモリ、および該マルチポートメモリを備えるコンピュータシステム
JP5449686B2 (ja) * 2008-03-21 2014-03-19 ピーエスフォー ルクスコ エスエイアールエル マルチポートメモリ及びそのマルチポートメモリを用いたシステム
JP5588100B2 (ja) * 2008-06-23 2014-09-10 ピーエスフォー ルクスコ エスエイアールエル 半導体装置およびデータ処理システム
US8713248B2 (en) * 2009-06-02 2014-04-29 Nokia Corporation Memory device and method for dynamic random access memory having serial interface and integral instruction buffer
US9003206B2 (en) * 2009-12-23 2015-04-07 Bae Systems Information And Electronic Systems Integration Inc. Managing communication and control of power components
US8547774B2 (en) 2010-01-29 2013-10-01 Mosys, Inc. Hierarchical multi-bank multi-port memory organization
CN102193865B (zh) * 2010-03-16 2015-03-25 联想(北京)有限公司 存储系统、存储方法和使用其的终端
US8718806B2 (en) 2011-09-02 2014-05-06 Apple Inc. Slave mode transmit with zero delay for audio interface
US9514069B1 (en) 2012-05-24 2016-12-06 Schwegman, Lundberg & Woessner, P.A. Enhanced computer processor and memory management architecture
EP3454594B1 (en) 2013-06-11 2020-11-04 Seven Networks, LLC Offloading application traffic to a shared communication channel for signal optimisation in a wireless network for traffic utilizing proprietary and non-proprietary protocols
CN104717152B (zh) * 2013-12-17 2019-07-19 深圳市中兴微电子技术有限公司 一种实现接口缓存动态分配的方法和装置
CN106293635B (zh) * 2015-05-13 2018-10-30 华为技术有限公司 指令块处理方法及装置
US9965211B2 (en) 2016-09-08 2018-05-08 Cisco Technology, Inc. Dynamic packet buffers with consolidation of low utilized memory banks
KR20180092476A (ko) * 2017-02-09 2018-08-20 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
CN109582226A (zh) * 2018-11-14 2019-04-05 北京中电华大电子设计有限责任公司 一种高速存储访问逻辑结构及其控制方法
US11385837B2 (en) 2020-01-07 2022-07-12 SK Hynix Inc. Memory system
TW202141290A (zh) 2020-01-07 2021-11-01 韓商愛思開海力士有限公司 記憶體中處理(pim)系統和pim系統的操作方法
US11315611B2 (en) * 2020-01-07 2022-04-26 SK Hynix Inc. Processing-in-memory (PIM) system and operating methods of the PIM system
CN115065572B (zh) * 2022-02-28 2023-09-29 西安电子科技大学 一种面向车载电子系统的can fd控制器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450355A (en) * 1993-02-05 1995-09-12 Micron Semiconductor, Inc. Multi-port memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
EP0471932B1 (en) * 1990-07-27 1997-01-22 International Business Machines Corporation Virtual multi-port ram
US5581773A (en) * 1992-05-12 1996-12-03 Glover; Michael A. Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements
US5490112A (en) * 1993-02-05 1996-02-06 Micron Technology, Inc. Multi-port memory device with multiple sets of columns
JPH06251166A (ja) * 1993-02-25 1994-09-09 Toshiba Corp 画像処理装置
US5442747A (en) * 1993-09-27 1995-08-15 Auravision Corporation Flexible multiport multiformat burst buffer
US5457654A (en) * 1994-07-26 1995-10-10 Micron Technology, Inc. Memory circuit for pre-loading a serial pipeline

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450355A (en) * 1993-02-05 1995-09-12 Micron Semiconductor, Inc. Multi-port memory device

Also Published As

Publication number Publication date
HK1018342A1 (en) 1999-12-17
CN1120495C (zh) 2003-09-03
AU6529596A (en) 1997-07-28
US5799209A (en) 1998-08-25
IL125135A (en) 2002-12-01
EP0870303B1 (en) 2000-10-18
ATE197101T1 (de) 2000-11-15
DK0870303T3 (da) 2001-02-26
WO1997024725A1 (en) 1997-07-10
CA2241841A1 (en) 1997-07-10
DE69610714T2 (de) 2001-05-10
EP0870303A1 (en) 1998-10-14
KR19990076893A (ko) 1999-10-25
CA2241841C (en) 1999-10-26
JP2000501524A (ja) 2000-02-08
KR100328603B1 (ko) 2002-10-19
DE69610714D1 (de) 2000-11-23
US6108725A (en) 2000-08-22
IL125135A0 (en) 1999-01-26
CN1209213A (zh) 1999-02-24
GR3035261T3 (en) 2001-04-30
TW318222B (zh) 1997-10-21
JP3699126B2 (ja) 2005-09-28

Similar Documents

Publication Publication Date Title
AU721764B2 (en) High performance universal multi-port internally cached dynamic random access memory system, architecture and method
WO1997024725A9 (en) High performance universal multi-port internally cached dynamic random access memory system, architecture and method
KR100272072B1 (ko) 동기형 다이나믹 램들을 활용한 고성능, 고대역폭 메모리 버스구조체
US6088774A (en) Read/write timing for maximum utilization of bidirectional read/write bus
US6366583B2 (en) Network router integrated onto a silicon chip
EP1237337B1 (en) Efficient optimization algorithm in memory utilization for network applications
US6212597B1 (en) Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like
US6920512B2 (en) Computer architecture and system for efficient management of bi-directional bus
JP3383846B2 (ja) マルチポートram用の拡張可能なデータ幅を有するsam
US6920510B2 (en) Time sharing a single port memory among a plurality of ports
KR100310568B1 (ko) 랜덤액세스메모리장치,랜덤액세스메모리제어기,랜덤액세스메모리의동시판독및기록방법
CN114442908B (zh) 一种用于数据处理的硬件加速系统及芯片
US7523250B2 (en) Semiconductor memory system and semiconductor memory chip
JP2000030452A (ja) コマンド・スタッキングを有する高帯域幅で狭い入出力のメモリ装置
US7324546B1 (en) Network router integrated onto a silicon chip
US20030093594A1 (en) Apparatus and method for controlling block signal flow in a multi digital signal processor configuration from a shared peripheral direct memory controller to high level data link controller
JP2546743B2 (ja) 音声およびデータのためのパケット/高速パケット交換機
WO1996019772A1 (en) Variable data processor allocation and memory sharing
JP3651672B2 (ja) 演算処理システム、特に通信装置のための演算処理システム
KR100876537B1 (ko) 멀티 파라메터 셋을 이용한 디엠에이 콘트롤러 장치 및제어 방법
KR100599504B1 (ko) 화면 표시 장치를 위한 단일 입출력 메모리 구조의 효과적제어 방법
JP2000148697A (ja) コンピュ―タ・システム
JPH10312355A (ja) 制御ユニット及び通信システム

Legal Events

Date Code Title Description
FGA Letters patent sealed or granted (standard patent)