AU696107B2 - Improved isolation between diffusion lines in a memory array - Google Patents

Improved isolation between diffusion lines in a memory array

Info

Publication number
AU696107B2
AU696107B2 AU35109/95A AU3510995A AU696107B2 AU 696107 B2 AU696107 B2 AU 696107B2 AU 35109/95 A AU35109/95 A AU 35109/95A AU 3510995 A AU3510995 A AU 3510995A AU 696107 B2 AU696107 B2 AU 696107B2
Authority
AU
Australia
Prior art keywords
strips
layer
conductive layer
patterning
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU35109/95A
Other languages
English (en)
Other versions
AU3510995A (en
Inventor
Tong-Chern Ong
Daniel N Tang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU3510995A publication Critical patent/AU3510995A/en
Application granted granted Critical
Publication of AU696107B2 publication Critical patent/AU696107B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10W10/0124—
    • H10W10/0126—
    • H10W10/0128—
    • H10W10/13—

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Building Environments (AREA)
  • Thermal Insulation (AREA)
AU35109/95A 1994-09-30 1995-09-13 Improved isolation between diffusion lines in a memory array Ceased AU696107B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US315876 1994-09-30
US08/315,876 US5466624A (en) 1994-09-30 1994-09-30 Isolation between diffusion lines in a memory array
PCT/US1995/011563 WO1996010840A1 (en) 1994-09-30 1995-09-13 Improved isolation between diffusion lines in a memory array

Publications (2)

Publication Number Publication Date
AU3510995A AU3510995A (en) 1996-04-26
AU696107B2 true AU696107B2 (en) 1998-09-03

Family

ID=23226447

Family Applications (1)

Application Number Title Priority Date Filing Date
AU35109/95A Ceased AU696107B2 (en) 1994-09-30 1995-09-13 Improved isolation between diffusion lines in a memory array

Country Status (7)

Country Link
US (1) US5466624A (enExample)
EP (1) EP0731983B1 (enExample)
AT (1) ATE228719T1 (enExample)
AU (1) AU696107B2 (enExample)
DE (1) DE69528962T2 (enExample)
TW (1) TW282581B (enExample)
WO (1) WO1996010840A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3159850B2 (ja) * 1993-11-08 2001-04-23 シャープ株式会社 不揮発性半導体記憶装置及びその製造方法
JP3445660B2 (ja) * 1994-07-08 2003-09-08 新日本製鐵株式会社 不揮発性半導体記憶装置及びその製造方法
US5536670A (en) * 1994-08-09 1996-07-16 United Microelectronics Corporation Process for making a buried bit line memory cell
JPH09293842A (ja) * 1996-04-26 1997-11-11 Ricoh Co Ltd 半導体記憶装置の製造方法
TW351859B (en) * 1996-06-29 1999-02-01 United Microelectronics Corp Method for fabrication high density masked ROM
DE19704503C1 (de) * 1997-02-06 1998-04-09 Siemens Ag Steckverbindung für einen Stapel kartenförmiger Datenträgeranordnungen
US5895241A (en) * 1997-03-28 1999-04-20 Lu; Tao Cheng Method for fabricating a cell structure for mask ROM
US5976927A (en) * 1998-04-10 1999-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Two mask method for reducing field oxide encroachment in memory arrays
US6133097A (en) 1998-08-14 2000-10-17 Taiwan Semiconductor Manufacturing Company Method for forming mirror image split gate flash memory devices by forming a central source line slot
KR100317492B1 (ko) * 1999-12-28 2001-12-24 박종섭 플래쉬 메모리 소자의 코드저장 셀
DE10332095B3 (de) * 2003-07-15 2005-01-20 Infineon Technologies Ag Halbleiterspeicher mit Charge-trapping-Speicherzellen
IT1401729B1 (it) * 2010-06-17 2013-08-02 St Microelectronics Srl Procedimento per la fabbricazione di dispositivi integrati di potenza con corrugazioni superficiali e dispositivo integrato di potenza con corrugazioni superficiali

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
US5075245A (en) * 1990-08-03 1991-12-24 Intel Corporation Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps
US5330938A (en) * 1989-12-22 1994-07-19 Sgs-Thomson Microelectronics S.R.L. Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
JPH0797606B2 (ja) * 1986-10-22 1995-10-18 株式会社日立製作所 半導体集積回路装置の製造方法
IT1228720B (it) * 1989-03-15 1991-07-03 Sgs Thomson Microelectronics Matrice a tovaglia di celle di memoria eprom con giunzioni sepolte, accessibili singolarmente mediante decodifica tradizionale.
US5102814A (en) * 1990-11-02 1992-04-07 Intel Corporation Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions
US5120671A (en) * 1990-11-29 1992-06-09 Intel Corporation Process for self aligning a source region with a field oxide region and a polysilicon gate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
US5330938A (en) * 1989-12-22 1994-07-19 Sgs-Thomson Microelectronics S.R.L. Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation
US5075245A (en) * 1990-08-03 1991-12-24 Intel Corporation Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps

Also Published As

Publication number Publication date
AU3510995A (en) 1996-04-26
EP0731983A4 (en) 1997-11-26
EP0731983B1 (en) 2002-11-27
EP0731983A1 (en) 1996-09-18
DE69528962T2 (de) 2003-08-28
DE69528962D1 (de) 2003-01-09
US5466624A (en) 1995-11-14
ATE228719T1 (de) 2002-12-15
WO1996010840A1 (en) 1996-04-11
TW282581B (enExample) 1996-08-01

Similar Documents

Publication Publication Date Title
US5021848A (en) Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5019879A (en) Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
US5877523A (en) Multi-level split- gate flash memory cell
US5060195A (en) Hot electron programmable, tunnel electron erasable contactless EEPROM
US5284785A (en) Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and methods for making and using the same
US6514830B1 (en) Method of manufacturing high voltage transistor with modified field implant mask
KR100304710B1 (ko) 셀 어레이 영역내에 벌크 바이어스 콘택 구조를 구비하는 비휘발성 메모리소자
US5466622A (en) Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection
JPH05259475A (ja) メモリセルのアレイを含む電気的にプログラム可能な読出し専用メモリ装置をシリコン基板に製造する方法
JPH04229654A (ja) 無接点フローティングゲートメモリアレイを製造する方法
US6351008B1 (en) Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions
GB2248518A (en) A non-volatile semiconductor memory device having storage cell array and peripheral circuit
EP0573728B1 (en) Process for fabricating high density contactless EPROMs
US5469383A (en) Memory cell array having continuous-strip field-oxide regions
AU696107B2 (en) Improved isolation between diffusion lines in a memory array
US5354703A (en) EEPROM cell array with tight erase distribution
KR100297728B1 (ko) 플래쉬 메모리 소자의 제조방법 및 그에 의해 제조된 플래쉬 메모리 소자
US6020237A (en) Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures
US5894162A (en) High density EPROM cell and process for fabricating same
US5623443A (en) Scalable EPROM array with thick and thin non-field oxide gate insulators
US4951103A (en) Fast, trench isolated, planar flash EEPROMS with silicided bitlines
US6046085A (en) Elimination of poly stringers with straight poly profile
US6359305B1 (en) Trench-isolated EEPROM flash in segmented bit line page architecture
US5565371A (en) Method of making EPROM with separate erasing and programming regions
US6300194B1 (en) Method for manufacturing semiconductor integrated electronic memory devices having a virtual ground cells matrix