IT1228720B - Matrice a tovaglia di celle di memoria eprom con giunzioni sepolte, accessibili singolarmente mediante decodifica tradizionale. - Google Patents

Matrice a tovaglia di celle di memoria eprom con giunzioni sepolte, accessibili singolarmente mediante decodifica tradizionale.

Info

Publication number
IT1228720B
IT1228720B IT8919777A IT1977789A IT1228720B IT 1228720 B IT1228720 B IT 1228720B IT 8919777 A IT8919777 A IT 8919777A IT 1977789 A IT1977789 A IT 1977789A IT 1228720 B IT1228720 B IT 1228720B
Authority
IT
Italy
Prior art keywords
tablecloth
eprom
die
memory cells
traditional decoding
Prior art date
Application number
IT8919777A
Other languages
English (en)
Other versions
IT8919777A0 (it
Inventor
Stefano Mazzali
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8919777A priority Critical patent/IT1228720B/it
Publication of IT8919777A0 publication Critical patent/IT8919777A0/it
Priority to EP90200510A priority patent/EP0387936A1/en
Priority to US07/488,148 priority patent/US5028979A/en
Priority to JP2060154A priority patent/JP2678674B2/ja
Application granted granted Critical
Publication of IT1228720B publication Critical patent/IT1228720B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
IT8919777A 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con giunzioni sepolte, accessibili singolarmente mediante decodifica tradizionale. IT1228720B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8919777A IT1228720B (it) 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con giunzioni sepolte, accessibili singolarmente mediante decodifica tradizionale.
EP90200510A EP0387936A1 (en) 1989-03-15 1990-03-05 Table cloth matrix of EPROM memory cells with buried junctions, individually accessible by a traditional decoder
US07/488,148 US5028979A (en) 1989-03-15 1990-03-05 Table cloth matrix of EPROM memory cells with buried junctions, individually accessible by a traditional decoder
JP2060154A JP2678674B2 (ja) 1989-03-15 1990-03-13 Ｅｐｒｏｍメモリセル構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8919777A IT1228720B (it) 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con giunzioni sepolte, accessibili singolarmente mediante decodifica tradizionale.

Publications (2)

Publication Number Publication Date
IT8919777A0 IT8919777A0 (it) 1989-03-15
IT1228720B true IT1228720B (it) 1991-07-03

Family

ID=11161130

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8919777A IT1228720B (it) 1989-03-15 1989-03-15 Matrice a tovaglia di celle di memoria eprom con giunzioni sepolte, accessibili singolarmente mediante decodifica tradizionale.

Country Status (4)

Country Link
US (1) US5028979A (it)
EP (1) EP0387936A1 (it)
JP (1) JP2678674B2 (it)
IT (1) IT1228720B (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088316B2 (ja) * 1990-01-31 1996-01-29 株式会社東芝 紫外線消去型不揮発性半導体メモリ装置
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing
US5289026A (en) * 1991-08-14 1994-02-22 Intel Corporation Asymmetric floating gate overlap for improved device characteristics in buried bit-line devices
EP1032034A1 (en) * 1992-01-22 2000-08-30 Macronix International Co., Ltd. Method of making memory device
US5526307A (en) * 1992-01-22 1996-06-11 Macronix International Co., Ltd. Flash EPROM integrated circuit architecture
US5618742A (en) * 1992-01-22 1997-04-08 Macronix Internatioal, Ltd. Method of making flash EPROM with conductive sidewall spacer contacting floating gate
JP3474614B2 (ja) * 1993-12-14 2003-12-08 マクロニクス インターナショナル カンパニイ リミテッド 不揮発性半導体メモリ装置及びその動作方法
US5466624A (en) * 1994-09-30 1995-11-14 Intel Corporation Isolation between diffusion lines in a memory array
EP0830684B1 (en) * 1995-06-07 2004-08-25 Macronix International Co., Ltd. Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width
US6580120B2 (en) * 2001-06-07 2003-06-17 Interuniversitair Microelektronica Centrum (Imec Vzw) Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits
US20070166903A1 (en) * 2006-01-17 2007-07-19 Bohumil Lojek Semiconductor structures formed by stepperless manufacturing

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258466A (en) * 1978-11-02 1981-03-31 Texas Instruments Incorporated High density electrically programmable ROM
US4342099A (en) * 1979-06-18 1982-07-27 Texas Instruments Incorporated Electrically erasable programmable MNOS read only memory
US4376947A (en) * 1979-09-04 1983-03-15 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
JPS56108259A (en) * 1980-02-01 1981-08-27 Hitachi Ltd Semiconductor memory device
JPS5728364A (en) * 1980-07-28 1982-02-16 Fujitsu Ltd Semiconductor memory device
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
JPS61222159A (ja) * 1985-01-30 1986-10-02 テキサス　インスツルメンツ　インコ−ポレイテツド 電気的にプログラム可能なメモリ・セル
US4750024A (en) * 1986-02-18 1988-06-07 Texas Instruments Incorporated Offset floating gate EPROM memory cell
US4892840A (en) * 1986-03-27 1990-01-09 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
JPS63281469A (ja) * 1987-05-13 1988-11-17 Seiko Instr & Electronics Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP0387936A1 (en) 1990-09-19
US5028979A (en) 1991-07-02
IT8919777A0 (it) 1989-03-15
JP2678674B2 (ja) 1997-11-17
JPH02291168A (ja) 1990-11-30

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970329