AU4561200A - Method for handling thinned chips for introducing them into chip cards - Google Patents

Method for handling thinned chips for introducing them into chip cards

Info

Publication number
AU4561200A
AU4561200A AU45612/00A AU4561200A AU4561200A AU 4561200 A AU4561200 A AU 4561200A AU 45612/00 A AU45612/00 A AU 45612/00A AU 4561200 A AU4561200 A AU 4561200A AU 4561200 A AU4561200 A AU 4561200A
Authority
AU
Australia
Prior art keywords
introducing
chip cards
thinned chips
handling thinned
handling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU45612/00A
Other languages
English (en)
Inventor
Thomas Grassl
Yahya Haghiri-Tehrani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Giesecke and Devrient GmbH
Original Assignee
Giesecke and Devrient GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giesecke and Devrient GmbH filed Critical Giesecke and Devrient GmbH
Publication of AU4561200A publication Critical patent/AU4561200A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/699—Insulating or insulated package substrates; Interposers; Redistribution layers for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
AU45612/00A 1999-05-07 2000-05-04 Method for handling thinned chips for introducing them into chip cards Abandoned AU4561200A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19921230 1999-05-07
DE19921230A DE19921230B4 (de) 1999-05-07 1999-05-07 Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten
PCT/EP2000/003988 WO2000068990A1 (de) 1999-05-07 2000-05-04 Verfahren zum handhaben von gedünnten chips zum einbringen in chipkarten

Publications (1)

Publication Number Publication Date
AU4561200A true AU4561200A (en) 2000-11-21

Family

ID=7907399

Family Applications (1)

Application Number Title Priority Date Filing Date
AU45612/00A Abandoned AU4561200A (en) 1999-05-07 2000-05-04 Method for handling thinned chips for introducing them into chip cards

Country Status (6)

Country Link
EP (1) EP1183726A1 (https=)
JP (1) JP2002544669A (https=)
CN (1) CN1157779C (https=)
AU (1) AU4561200A (https=)
DE (1) DE19921230B4 (https=)
WO (1) WO2000068990A1 (https=)

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DE10117880B4 (de) * 2001-04-10 2009-01-29 Mühlbauer Ag Verfahren zum Vereinzeln von elektronischen Bauteilen aus einem Verbund
US6964086B2 (en) * 2002-03-04 2005-11-15 Matsushita Electric Industrial Co., Ltd. Method of manufacturing thin film piezoelectric element, and element housing jig
US6943056B2 (en) 2002-04-16 2005-09-13 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
JP2004273895A (ja) * 2003-03-11 2004-09-30 Disco Abrasive Syst Ltd 半導体ウエーハの分割方法
DE10339559B4 (de) * 2003-08-26 2006-03-02 W.C. Heraeus Gmbh Verfahren zur Lagebestimmung von Bauelementträgern
DE10341186A1 (de) * 2003-09-06 2005-03-31 Martin Michalk Verfahren und Vorrichtung zum Kontaktieren von Halbleiterchips
GB2412786A (en) * 2004-03-24 2005-10-05 E2V Tech Uk Ltd Method and apparatus for manufacturing chip scale components or microcomponents
KR20070039126A (ko) * 2004-07-09 2007-04-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｉｃ칩 및 그 제조방법
DE102004036962A1 (de) * 2004-07-30 2006-03-23 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von Halbleiterchips in Dünnfilmtechnik und Halbleiterchip in Dünnfilmtechnik
JP5305655B2 (ja) 2004-07-30 2013-10-02 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング 薄膜技術による半導体チップの製造方法および薄膜半導体チップ
US8728937B2 (en) 2004-07-30 2014-05-20 Osram Opto Semiconductors Gmbh Method for producing semiconductor chips using thin film technology
FR2878076B1 (fr) * 2004-11-17 2007-02-23 St Microelectronics Sa Amincissement d'une plaquette semiconductrice
DE102004059599B3 (de) * 2004-12-09 2006-08-17 Infineon Technologies Ag Verfahren zum Aufbringen einer Klebstoffschicht auf dünngeschliffene Halbleiterchips eines Halbleiterwafers
DE102006032821B4 (de) * 2006-07-14 2008-04-10 Mühlbauer Ag Verfahren und Vorrichtung zur Herstellung einer Vielzahl von Chipkarten mit einer klebstofffreien Fixierung der Chipmodule
JP5248518B2 (ja) * 2006-11-24 2013-07-31 フラウンホッファー−ゲゼルシャフト・ツァー・フォデラング・デル・アンゲワンテン・フォーシュング・エー．ファウ． 電子、特に微細電子機能群とその製造方法
JP4958287B2 (ja) * 2007-05-30 2012-06-20 東京応化工業株式会社 剥がし装置における剥離方法
DE102010025774A1 (de) 2010-07-01 2012-01-05 Giesecke & Devrient Gmbh Verfahren zur Herstellung eines Inlays für einen tragbaren Datenträger und Inlay
JP6417164B2 (ja) * 2014-09-18 2018-10-31 芝浦メカトロニクス株式会社 積層体製造装置、積層体、分離装置及び積層体製造方法
CN114334678A (zh) * 2020-09-30 2022-04-12 日月光半导体制造股份有限公司 形成半导体封装结构的方法

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Also Published As

Publication number Publication date
DE19921230A1 (de) 2000-11-09
CN1157779C (zh) 2004-07-14
JP2002544669A (ja) 2002-12-24
DE19921230B4 (de) 2009-04-02
WO2000068990A1 (de) 2000-11-16
EP1183726A1 (de) 2002-03-06
CN1350701A (zh) 2002-05-22

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase