AU2014203283B2 - A filtered radiation hardened flip flop with reduced power consumption - Google Patents
A filtered radiation hardened flip flop with reduced power consumption Download PDFInfo
- Publication number
- AU2014203283B2 AU2014203283B2 AU2014203283A AU2014203283A AU2014203283B2 AU 2014203283 B2 AU2014203283 B2 AU 2014203283B2 AU 2014203283 A AU2014203283 A AU 2014203283A AU 2014203283 A AU2014203283 A AU 2014203283A AU 2014203283 B2 AU2014203283 B2 AU 2014203283B2
- Authority
- AU
- Australia
- Prior art keywords
- stage
- flip flop
- input
- gate
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Pulse Circuits (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/024,310 | 2013-09-11 | ||
| US14/024,310 US9013219B2 (en) | 2013-09-11 | 2013-09-11 | Filtered radiation hardened flip flop with reduced power consumption |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| AU2014203283A1 AU2014203283A1 (en) | 2015-03-26 |
| AU2014203283B2 true AU2014203283B2 (en) | 2018-10-18 |
Family
ID=52625008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2014203283A Active AU2014203283B2 (en) | 2013-09-11 | 2014-06-17 | A filtered radiation hardened flip flop with reduced power consumption |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9013219B2 (enExample) |
| JP (1) | JP6438237B2 (enExample) |
| CN (1) | CN104426532B (enExample) |
| AU (1) | AU2014203283B2 (enExample) |
| SG (1) | SG10201405181VA (enExample) |
| TW (1) | TWI631825B (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11374567B2 (en) * | 2017-02-11 | 2022-06-28 | Klas Olof Lilja | Circuit for low power, radiation hard logic cell |
| SG11202005673VA (en) * | 2017-12-29 | 2020-07-29 | Bae Systems | Radiation-hardened d flip-flop circuit |
| CN111656688B (zh) | 2018-01-22 | 2024-12-31 | 卓思私人有限公司 | 用于设定电路晶体管的宽长比的方法、电路及电路布置 |
| CN112119591B (zh) | 2018-03-19 | 2024-12-20 | 南洋理工大学 | 电路布置及其形成方法 |
| WO2019235363A1 (ja) * | 2018-06-04 | 2019-12-12 | 国立大学法人京都工芸繊維大学 | D型フリップフロップ回路 |
| US12294363B2 (en) | 2019-10-08 | 2025-05-06 | Zero-Error Systems Pte. Ltd | Circuit for mitigating single-event-transients |
| US11177795B1 (en) * | 2020-04-22 | 2021-11-16 | Xilinx, Inc. | Master latch design for single event upset flip-flop |
| US11601119B2 (en) | 2020-12-18 | 2023-03-07 | The Boeing Company | Radiation hardened flip-flop circuit for mitigating single event transients |
| CN112737560B (zh) * | 2020-12-24 | 2022-09-13 | 中国人民解放军国防科技大学 | 一种无频率损耗的集成电路抗单粒子瞬态加固方法 |
| JP2023034938A (ja) * | 2021-08-31 | 2023-03-13 | ローム株式会社 | フリップフロップ回路、半導体集積回路装置、及び車両 |
| CN120567108B (zh) * | 2025-07-30 | 2025-10-03 | 中国电子科技集团公司第五十八研究所 | 一种基于互连线串扰计算的抗辐照d触发器 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110102042A1 (en) * | 2007-09-19 | 2011-05-05 | International Business Machines Corporation | Apparatus and method for hardening latches in soi cmos devices |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0786170A1 (en) * | 1995-08-14 | 1997-07-30 | Koninklijke Philips Electronics N.V. | Mos master-slave flip-flop with reduced number of pass gates |
| JP2001237675A (ja) * | 2000-02-24 | 2001-08-31 | Ando Electric Co Ltd | D−ff回路 |
| US7523371B2 (en) * | 2004-06-30 | 2009-04-21 | Intel Corporation | System and shadow bistable circuits coupled to output joining circuit |
| JP4551731B2 (ja) * | 2004-10-15 | 2010-09-29 | 株式会社東芝 | 半導体集積回路 |
| US20060267653A1 (en) | 2005-05-25 | 2006-11-30 | Honeywell International Inc. | Single-event-effect hardened circuitry |
| JP4332652B2 (ja) * | 2005-12-12 | 2009-09-16 | 独立行政法人 宇宙航空研究開発機構 | シングルイベント耐性のラッチ回路及びフリップフロップ回路 |
| US8767444B2 (en) * | 2006-03-27 | 2014-07-01 | Honeywell International Inc. | Radiation-hardened memory element with multiple delay elements |
| US20080115023A1 (en) * | 2006-10-27 | 2008-05-15 | Honeywell International Inc. | Set hardened register |
| US7795927B2 (en) | 2007-08-17 | 2010-09-14 | Raytheon Company | Digital circuits with adaptive resistance to single event upset |
| KR20090131010A (ko) * | 2008-06-17 | 2009-12-28 | 주식회사 동부하이텍 | 듀얼 모드 에지 트리거 플립플롭 |
| CN101499788A (zh) * | 2009-02-19 | 2009-08-05 | 上海交通大学 | 抗单粒子翻转和单粒子瞬态脉冲的d触发器 |
| JP5372613B2 (ja) * | 2009-06-18 | 2013-12-18 | 株式会社日立製作所 | フリップフロップ、半導体集積回路、半導体デバイスおよびブレードサーバ |
| US8054099B2 (en) * | 2009-07-29 | 2011-11-08 | The Boeing Company | Method and apparatus for reducing radiation and cross-talk induced data errors |
| JP2012023436A (ja) * | 2010-07-12 | 2012-02-02 | Nippon Telegr & Teleph Corp <Ntt> | 多チャンネルosnrモニタ |
| US8493120B2 (en) * | 2011-03-10 | 2013-07-23 | Arm Limited | Storage circuitry and method with increased resilience to single event upsets |
| CN102394595B (zh) * | 2011-10-21 | 2013-12-11 | 中国人民解放军国防科学技术大学 | 抗单粒子翻转的可置位和复位d触发器 |
-
2013
- 2013-09-11 US US14/024,310 patent/US9013219B2/en active Active
-
2014
- 2014-06-17 AU AU2014203283A patent/AU2014203283B2/en active Active
- 2014-06-18 TW TW103120996A patent/TWI631825B/zh active
- 2014-08-25 SG SG10201405181VA patent/SG10201405181VA/en unknown
- 2014-08-28 JP JP2014173585A patent/JP6438237B2/ja active Active
- 2014-09-11 CN CN201410462302.0A patent/CN104426532B/zh active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110102042A1 (en) * | 2007-09-19 | 2011-05-05 | International Business Machines Corporation | Apparatus and method for hardening latches in soi cmos devices |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI631825B (zh) | 2018-08-01 |
| US9013219B2 (en) | 2015-04-21 |
| JP2015056892A (ja) | 2015-03-23 |
| AU2014203283A1 (en) | 2015-03-26 |
| TW201524123A (zh) | 2015-06-16 |
| US20150070062A1 (en) | 2015-03-12 |
| SG10201405181VA (en) | 2015-04-29 |
| CN104426532A (zh) | 2015-03-18 |
| JP6438237B2 (ja) | 2018-12-12 |
| CN104426532B (zh) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| AU2014203283B2 (en) | A filtered radiation hardened flip flop with reduced power consumption | |
| US8054099B2 (en) | Method and apparatus for reducing radiation and cross-talk induced data errors | |
| US7999567B2 (en) | SEU tolerant arbiter | |
| US20090256593A1 (en) | Programmable sample clock for empirical setup time selection | |
| CN106487361B (zh) | 具有共享的时钟开关的多位触发器 | |
| US8797077B2 (en) | Master-slave flip-flop circuit | |
| CN108233894B (zh) | 一种基于双模冗余的低功耗双边沿触发器 | |
| CN104009736A (zh) | 低功耗主从触发器 | |
| EP3308462A1 (en) | Feedback latch circuit | |
| US20210257999A1 (en) | Radiation-hardened d flip-flop circuit | |
| US10585143B2 (en) | Flip flop of a digital electronic chip | |
| CN103475359B (zh) | 抗单粒子瞬态脉冲cmos电路 | |
| US10181851B2 (en) | Dual interlocked logic circuits | |
| JP5627691B2 (ja) | 準安定性強化格納回路のための装置および関連する方法 | |
| Devarapalli et al. | SEU-hardened dual data rate flip-flop using C-elements | |
| CN103546146B (zh) | 抗单粒子瞬态脉冲cmos电路 | |
| CN103546145A (zh) | 抗单粒子瞬态脉冲cmos电路 | |
| JP5457727B2 (ja) | 半導体集積回路装置 | |
| Dash et al. | SEU hardened clock regeneration circuits | |
| Abhishek et al. | Low Power DET Flip-Flops Using C-Element | |
| CN103888099A (zh) | 一种抗单粒子瞬态冗余滤波器电路 | |
| Jagadeeswaran et al. | Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic | |
| Bandi et al. | Explicit pulse triggered flip flop design based on a signal feed-through scheme | |
| Narmatha et al. | Analysis of power optimization using SVL technique | |
| 陈刚 et al. | A dual redundancy radiation-hardened flip–flop based on a C-element in a 65 nm process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FGA | Letters patent sealed or granted (standard patent) |