AU2003298137A1 - Method of detaching a thin film at moderate temperature after co-implantation - Google Patents

Method of detaching a thin film at moderate temperature after co-implantation

Info

Publication number
AU2003298137A1
AU2003298137A1 AU2003298137A AU2003298137A AU2003298137A1 AU 2003298137 A1 AU2003298137 A1 AU 2003298137A1 AU 2003298137 A AU2003298137 A AU 2003298137A AU 2003298137 A AU2003298137 A AU 2003298137A AU 2003298137 A1 AU2003298137 A1 AU 2003298137A1
Authority
AU
Australia
Prior art keywords
detaching
implantation
thin film
moderate temperature
moderate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003298137A
Other languages
English (en)
Other versions
AU2003298137A8 (en
Inventor
Nadia Ben Mohamed
Ian Cayrefourcq
Christelle Lagahe-Blanchard
Nguyet-Phuong Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of AU2003298137A8 publication Critical patent/AU2003298137A8/xx
Publication of AU2003298137A1 publication Critical patent/AU2003298137A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
AU2003298137A 2002-11-07 2003-10-30 Method of detaching a thin film at moderate temperature after co-implantation Abandoned AU2003298137A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR02/13935 2002-11-07
FR0213935A FR2847076B1 (fr) 2002-11-07 2002-11-07 Procede de detachement d'une couche mince a temperature moderee apres co-implantation
PCT/EP2003/013148 WO2004042779A2 (en) 2002-11-07 2003-10-30 Method of detaching a thin film at moderate temperature after co-implantation

Publications (2)

Publication Number Publication Date
AU2003298137A8 AU2003298137A8 (en) 2004-06-07
AU2003298137A1 true AU2003298137A1 (en) 2004-06-07

Family

ID=32116442

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003298137A Abandoned AU2003298137A1 (en) 2002-11-07 2003-10-30 Method of detaching a thin film at moderate temperature after co-implantation

Country Status (8)

Country Link
EP (1) EP1559139B1 (enExample)
JP (2) JP4999272B2 (enExample)
KR (1) KR101122859B1 (enExample)
CN (1) CN1708843B (enExample)
AU (1) AU2003298137A1 (enExample)
FR (1) FR2847076B1 (enExample)
TW (1) TWI294663B (enExample)
WO (1) WO2004042779A2 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
EP1605504B1 (en) * 2004-06-10 2011-05-25 S.O.I. Tec Silicon on Insulator Technologies S.A. Method for manufacturing a SOI wafer
CN100527416C (zh) * 2004-08-18 2009-08-12 康宁股份有限公司 应变绝缘体上半导体结构以及应变绝缘体上半导体结构的制造方法
CN101027768B (zh) * 2004-09-21 2010-11-03 S.O.I.Tec绝缘体上硅技术公司 根据避免气泡形成和限制粗糙度的条件来进行共注入步骤的薄层转移方法
DE602004027422D1 (de) * 2004-09-21 2010-07-08 Soitec Silicon On Insulator Übertragungsverfahren mit einer behandlung einer zu verbindenden oberfläche
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2907966B1 (fr) 2006-10-27 2009-01-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat.
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
KR100873299B1 (ko) * 2007-08-20 2008-12-11 주식회사 실트론 Ｓｓｏｉ 기판의 제조방법
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
FR2949606B1 (fr) 2009-08-26 2011-10-28 Commissariat Energie Atomique Procede de detachement par fracture d'un film mince de silicium mettant en oeuvre une triple implantation
FR2974944B1 (fr) * 2011-05-02 2013-06-14 Commissariat Energie Atomique Procédé de formation d'une fracture dans un matériau
KR101219358B1 (ko) * 2011-07-26 2013-01-21 삼성코닝정밀소재 주식회사 기판 분리 방법 및 이를 이용한 접합기판 제조방법
FR3045678B1 (fr) 2015-12-22 2017-12-22 Soitec Silicon On Insulator Procede de fabrication d'une couche piezoelectrique monocristalline et dispositif microelectronique, photonique ou optique comprenant une telle couche
FR3045677B1 (fr) 2015-12-22 2019-07-19 Soitec Procede de fabrication d'une couche monocristalline, notamment piezoelectrique
JP6563360B2 (ja) * 2016-04-05 2019-08-21 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
CN106222754A (zh) * 2016-07-29 2016-12-14 成都立威讯科技有限公司 一种工艺精湛的蓝宝石分离方法
DE102016118268B4 (de) * 2016-09-27 2025-06-26 Infineon Technologies Ag Verfahren zum Bearbeiten eines einkristallinen Substrats und mikromechanische Struktur
WO2020247531A1 (en) * 2019-06-06 2020-12-10 Applied Materials, Inc. Methods of post treating silicon nitride based dielectric films with high energy low dose plasma
FR3108440B1 (fr) * 2020-03-23 2025-01-17 Soitec Silicon On Insulator Procédé de préparation d’une couche mince

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2738671B1 (fr) * 1995-09-13 1997-10-10 Commissariat Energie Atomique Procede de fabrication de films minces a materiau semiconducteur
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
JP3412470B2 (ja) * 1997-09-04 2003-06-03 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
JPH11307747A (ja) * 1998-04-17 1999-11-05 Nec Corp Ｓｏｉ基板およびその製造方法
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
US6600173B2 (en) * 2000-08-30 2003-07-29 Cornell Research Foundation, Inc. Low temperature semiconductor layering and three-dimensional electronic circuits using the layering

Also Published As

Publication number Publication date
FR2847076B1 (fr) 2005-02-18
JP2006505928A (ja) 2006-02-16
EP1559139A2 (en) 2005-08-03
KR20050060111A (ko) 2005-06-21
AU2003298137A8 (en) 2004-06-07
FR2847076A1 (fr) 2004-05-14
WO2004042779A3 (en) 2004-09-23
TW200423295A (en) 2004-11-01
KR101122859B1 (ko) 2012-03-21
JP4999272B2 (ja) 2012-08-15
JP2012084897A (ja) 2012-04-26
TWI294663B (en) 2008-03-11
WO2004042779A2 (en) 2004-05-21
EP1559139B1 (en) 2013-05-29
CN1708843B (zh) 2010-08-18
CN1708843A (zh) 2005-12-14

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase
TH Corrigenda

Free format text: IN VOL 18, NO 25, PAGE(S) 7007 UNDER THE HEADING APPLICATIONS OPI - NAME INDEX UNDER THE NAME S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, APPLICATION NO. 2003298137, UNDER INID (71) CORRECT THE NAME TO READ COMMISSARIAT A L ENERGIE ATOMIQUE; S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES