ATE68912T1 - Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid. - Google Patents

Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid.

Info

Publication number
ATE68912T1
ATE68912T1 AT86905124T AT86905124T ATE68912T1 AT E68912 T1 ATE68912 T1 AT E68912T1 AT 86905124 T AT86905124 T AT 86905124T AT 86905124 T AT86905124 T AT 86905124T AT E68912 T1 ATE68912 T1 AT E68912T1
Authority
AT
Austria
Prior art keywords
polyimide
layer
sio2
region
etching
Prior art date
Application number
AT86905124T
Other languages
English (en)
Inventor
Michael Henry Nemiroff
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of ATE68912T1 publication Critical patent/ATE68912T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Spinning Methods And Devices For Manufacturing Artificial Fibers (AREA)
AT86905124T 1985-09-27 1986-08-15 Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid. ATE68912T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US78083385A 1985-09-27 1985-09-27
EP86905124A EP0241480B1 (de) 1985-09-27 1986-08-15 Verfahren zur herstellung einer konischen kontaktöffnung in polyimid
PCT/US1986/001676 WO1987002179A1 (en) 1985-09-27 1986-08-15 Method of fabricating a tapered via hole in polyimide

Publications (1)

Publication Number Publication Date
ATE68912T1 true ATE68912T1 (de) 1991-11-15

Family

ID=25120845

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86905124T ATE68912T1 (de) 1985-09-27 1986-08-15 Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid.

Country Status (7)

Country Link
US (1) US4832788A (de)
EP (1) EP0241480B1 (de)
JP (1) JPS62502646A (de)
AT (1) ATE68912T1 (de)
CA (1) CA1266724A (de)
DE (1) DE3682195D1 (de)
WO (1) WO1987002179A1 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3776325D1 (de) * 1987-04-16 1992-03-05 Ibm Verfahren zur herstellung von kontaktoeffnungen in einer doppellagenisolation.
JPH023938A (ja) * 1988-06-20 1990-01-09 Mitsubishi Electric Corp 電界効果トランジスタ
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
FR2669466B1 (fr) * 1990-11-16 1997-11-07 Michel Haond Procede de gravure de couches de circuit integre a profondeur fixee et circuit integre correspondant.
US5315312A (en) * 1991-05-06 1994-05-24 Copytele, Inc. Electrophoretic display panel with tapered grid insulators and associated methods
US5180689A (en) * 1991-09-10 1993-01-19 Taiwan Semiconductor Manufacturing Company Tapered opening sidewall with multi-step etching process
DE59209764D1 (de) * 1992-05-20 1999-12-09 Ibm Verfahren zum Erzeugen einer mehrstufigen Struktur in einem Substrat
US5308415A (en) * 1992-12-31 1994-05-03 Chartered Semiconductor Manufacturing Pte Ltd. Enhancing step coverage by creating a tapered profile through three dimensional resist pull back
US6475903B1 (en) 1993-12-28 2002-11-05 Intel Corporation Copper reflow process
US5593606A (en) * 1994-07-18 1997-01-14 Electro Scientific Industries, Inc. Ultraviolet laser system and method for forming vias in multi-layered targets
US5614114A (en) * 1994-07-18 1997-03-25 Electro Scientific Industries, Inc. Laser system and method for plating vias
US5841099A (en) * 1994-07-18 1998-11-24 Electro Scientific Industries, Inc. Method employing UV laser pulses of varied energy density to form depthwise self-limiting blind vias in multilayered targets
US5444007A (en) * 1994-08-03 1995-08-22 Kabushiki Kaisha Toshiba Formation of trenches having different profiles
US5654232A (en) * 1994-08-24 1997-08-05 Intel Corporation Wetting layer sidewalls to promote copper reflow into grooves
US5453403A (en) * 1994-10-24 1995-09-26 Chartered Semiconductor Manufacturing Pte, Ltd. Method of beveled contact opening formation
GB9600469D0 (en) 1996-01-10 1996-03-13 Secr Defence Three dimensional etching process
US5893758A (en) * 1996-06-26 1999-04-13 Micron Technology, Inc. Etching method for reducing cusping at openings
US5891803A (en) * 1996-06-26 1999-04-06 Intel Corporation Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits
GB9616225D0 (en) 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
EP1357584A3 (de) * 1996-08-01 2005-01-12 Surface Technology Systems Plc Verfahren zur Oberflachensbehandlung von halbleitenden Substraten
US6025256A (en) * 1997-01-06 2000-02-15 Electro Scientific Industries, Inc. Laser based method and system for integrated circuit repair or reconfiguration
US6187685B1 (en) 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
US5880030A (en) * 1997-11-25 1999-03-09 Intel Corporation Unlanded via structure and method for making same
US6143476A (en) * 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
TWI246633B (en) 1997-12-12 2006-01-01 Applied Materials Inc Method of pattern etching a low k dielectric layen
US6417013B1 (en) 1999-01-29 2002-07-09 Plasma-Therm, Inc. Morphed processing of semiconductor devices
SG112804A1 (en) * 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
JP4571785B2 (ja) * 2003-05-30 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7262123B2 (en) * 2004-07-29 2007-08-28 Micron Technology, Inc. Methods of forming wire bonds for semiconductor constructions
US7282802B2 (en) * 2004-10-14 2007-10-16 International Business Machines Corporation Modified via bottom structure for reliability enhancement
JP2019121750A (ja) * 2018-01-11 2019-07-22 東京エレクトロン株式会社 エッチング方法およびエッチング装置
US11189523B2 (en) * 2019-06-12 2021-11-30 Nanya Technology Corporation Semiconductor structure and fabrication method thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808069A (en) * 1972-03-15 1974-04-30 Bell Telephone Labor Inc Forming windows in composite dielectric layers
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US4514252A (en) * 1982-11-18 1985-04-30 Hewlett-Packard Company Technique of producing tapered features in integrated circuits
GB8312850D0 (en) * 1983-05-10 1983-06-15 British Telecomm Semiconductor wafer fabrication
US4495220A (en) * 1983-10-07 1985-01-22 Trw Inc. Polyimide inter-metal dielectric process
JPS60140720A (ja) * 1983-12-28 1985-07-25 Fujitsu Ltd 半導体装置およびその製造方法
US4487652A (en) * 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
FR2563048B1 (fr) * 1984-04-13 1986-05-30 Efcis Procede de realisation de contacts d'aluminium a travers une couche isolante epaisse dans un circuit integre
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4522681A (en) * 1984-04-23 1985-06-11 General Electric Company Method for tapered dry etching
US4560436A (en) * 1984-07-02 1985-12-24 Motorola, Inc. Process for etching tapered polyimide vias

Also Published As

Publication number Publication date
JPH0587132B2 (de) 1993-12-15
DE3682195D1 (de) 1991-11-28
JPS62502646A (ja) 1987-10-08
CA1266724A (en) 1990-03-13
US4832788A (en) 1989-05-23
WO1987002179A1 (en) 1987-04-09
EP0241480B1 (de) 1991-10-23
EP0241480A1 (de) 1987-10-21

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Legal Events

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