DE3682195D1 - Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid. - Google Patents
Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid.Info
- Publication number
- DE3682195D1 DE3682195D1 DE8686905124T DE3682195T DE3682195D1 DE 3682195 D1 DE3682195 D1 DE 3682195D1 DE 8686905124 T DE8686905124 T DE 8686905124T DE 3682195 T DE3682195 T DE 3682195T DE 3682195 D1 DE3682195 D1 DE 3682195D1
- Authority
- DE
- Germany
- Prior art keywords
- polyimide
- layer
- sio2
- region
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/95—Multilayer mask including nonradiation sensitive layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Spinning Methods And Devices For Manufacturing Artificial Fibers (AREA)
- Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US78083385A | 1985-09-27 | 1985-09-27 | |
PCT/US1986/001676 WO1987002179A1 (en) | 1985-09-27 | 1986-08-15 | Method of fabricating a tapered via hole in polyimide |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3682195D1 true DE3682195D1 (de) | 1991-11-28 |
Family
ID=25120845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686905124T Expired - Fee Related DE3682195D1 (de) | 1985-09-27 | 1986-08-15 | Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4832788A (de) |
EP (1) | EP0241480B1 (de) |
JP (1) | JPS62502646A (de) |
AT (1) | ATE68912T1 (de) |
CA (1) | CA1266724A (de) |
DE (1) | DE3682195D1 (de) |
WO (1) | WO1987002179A1 (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0286708B1 (de) * | 1987-04-16 | 1992-01-22 | International Business Machines Corporation | Verfahren zur Herstellung von Kontaktöffnungen in einer Doppellagenisolation |
JPH023938A (ja) * | 1988-06-20 | 1990-01-09 | Mitsubishi Electric Corp | 電界効果トランジスタ |
US4902377A (en) * | 1989-05-23 | 1990-02-20 | Motorola, Inc. | Sloped contact etch process |
FR2669466B1 (fr) * | 1990-11-16 | 1997-11-07 | Michel Haond | Procede de gravure de couches de circuit integre a profondeur fixee et circuit integre correspondant. |
US5315312A (en) * | 1991-05-06 | 1994-05-24 | Copytele, Inc. | Electrophoretic display panel with tapered grid insulators and associated methods |
US5180689A (en) * | 1991-09-10 | 1993-01-19 | Taiwan Semiconductor Manufacturing Company | Tapered opening sidewall with multi-step etching process |
EP0570609B1 (de) * | 1992-05-20 | 1999-11-03 | International Business Machines Corporation | Verfahren zum Erzeugen einer mehrstufigen Struktur in einem Substrat |
US5308415A (en) * | 1992-12-31 | 1994-05-03 | Chartered Semiconductor Manufacturing Pte Ltd. | Enhancing step coverage by creating a tapered profile through three dimensional resist pull back |
US6475903B1 (en) * | 1993-12-28 | 2002-11-05 | Intel Corporation | Copper reflow process |
US5614114A (en) * | 1994-07-18 | 1997-03-25 | Electro Scientific Industries, Inc. | Laser system and method for plating vias |
US5593606A (en) * | 1994-07-18 | 1997-01-14 | Electro Scientific Industries, Inc. | Ultraviolet laser system and method for forming vias in multi-layered targets |
US5841099A (en) * | 1994-07-18 | 1998-11-24 | Electro Scientific Industries, Inc. | Method employing UV laser pulses of varied energy density to form depthwise self-limiting blind vias in multilayered targets |
US5444007A (en) * | 1994-08-03 | 1995-08-22 | Kabushiki Kaisha Toshiba | Formation of trenches having different profiles |
US5654232A (en) * | 1994-08-24 | 1997-08-05 | Intel Corporation | Wetting layer sidewalls to promote copper reflow into grooves |
US5453403A (en) * | 1994-10-24 | 1995-09-26 | Chartered Semiconductor Manufacturing Pte, Ltd. | Method of beveled contact opening formation |
GB9600469D0 (en) | 1996-01-10 | 1996-03-13 | Secr Defence | Three dimensional etching process |
US5891803A (en) * | 1996-06-26 | 1999-04-06 | Intel Corporation | Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits |
US5893758A (en) * | 1996-06-26 | 1999-04-13 | Micron Technology, Inc. | Etching method for reducing cusping at openings |
GB9616225D0 (en) | 1996-08-01 | 1996-09-11 | Surface Tech Sys Ltd | Method of surface treatment of semiconductor substrates |
DE69725245T2 (de) * | 1996-08-01 | 2004-08-12 | Surface Technoloy Systems Plc | Verfahren zur Ätzung von Substraten |
US6025256A (en) * | 1997-01-06 | 2000-02-15 | Electro Scientific Industries, Inc. | Laser based method and system for integrated circuit repair or reconfiguration |
US6187685B1 (en) | 1997-08-01 | 2001-02-13 | Surface Technology Systems Limited | Method and apparatus for etching a substrate |
US5880030A (en) * | 1997-11-25 | 1999-03-09 | Intel Corporation | Unlanded via structure and method for making same |
TW505984B (en) | 1997-12-12 | 2002-10-11 | Applied Materials Inc | Method of etching patterned layers useful as masking during subsequent etching or for damascene structures |
US6143476A (en) * | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
US6417013B1 (en) | 1999-01-29 | 2002-07-09 | Plasma-Therm, Inc. | Morphed processing of semiconductor devices |
SG112804A1 (en) * | 2001-05-10 | 2005-07-28 | Inst Of Microelectronics | Sloped trench etching process |
JP4571785B2 (ja) * | 2003-05-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7262123B2 (en) * | 2004-07-29 | 2007-08-28 | Micron Technology, Inc. | Methods of forming wire bonds for semiconductor constructions |
US7282802B2 (en) * | 2004-10-14 | 2007-10-16 | International Business Machines Corporation | Modified via bottom structure for reliability enhancement |
JP2019121750A (ja) * | 2018-01-11 | 2019-07-22 | 東京エレクトロン株式会社 | エッチング方法およびエッチング装置 |
US11189523B2 (en) * | 2019-06-12 | 2021-11-30 | Nanya Technology Corporation | Semiconductor structure and fabrication method thereof |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3808069A (en) * | 1972-03-15 | 1974-04-30 | Bell Telephone Labor Inc | Forming windows in composite dielectric layers |
US4472240A (en) * | 1981-08-21 | 1984-09-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
US4514252A (en) * | 1982-11-18 | 1985-04-30 | Hewlett-Packard Company | Technique of producing tapered features in integrated circuits |
GB8312850D0 (en) * | 1983-05-10 | 1983-06-15 | British Telecomm | Semiconductor wafer fabrication |
US4495220A (en) * | 1983-10-07 | 1985-01-22 | Trw Inc. | Polyimide inter-metal dielectric process |
JPS60140720A (ja) * | 1983-12-28 | 1985-07-25 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US4487652A (en) * | 1984-03-30 | 1984-12-11 | Motorola, Inc. | Slope etch of polyimide |
FR2563048B1 (fr) * | 1984-04-13 | 1986-05-30 | Efcis | Procede de realisation de contacts d'aluminium a travers une couche isolante epaisse dans un circuit integre |
US4484979A (en) * | 1984-04-16 | 1984-11-27 | At&T Bell Laboratories | Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer |
US4522681A (en) * | 1984-04-23 | 1985-06-11 | General Electric Company | Method for tapered dry etching |
US4560436A (en) * | 1984-07-02 | 1985-12-24 | Motorola, Inc. | Process for etching tapered polyimide vias |
-
1986
- 1986-08-15 AT AT86905124T patent/ATE68912T1/de not_active IP Right Cessation
- 1986-08-15 DE DE8686905124T patent/DE3682195D1/de not_active Expired - Fee Related
- 1986-08-15 EP EP86905124A patent/EP0241480B1/de not_active Expired - Lifetime
- 1986-08-15 WO PCT/US1986/001676 patent/WO1987002179A1/en active IP Right Grant
- 1986-08-15 JP JP61504422A patent/JPS62502646A/ja active Granted
- 1986-09-19 CA CA000518649A patent/CA1266724A/en not_active Expired - Fee Related
-
1987
- 1987-05-21 US US07/053,554 patent/US4832788A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4832788A (en) | 1989-05-23 |
CA1266724A (en) | 1990-03-13 |
JPS62502646A (ja) | 1987-10-08 |
EP0241480B1 (de) | 1991-10-23 |
ATE68912T1 (de) | 1991-11-15 |
JPH0587132B2 (de) | 1993-12-15 |
EP0241480A1 (de) | 1987-10-21 |
WO1987002179A1 (en) | 1987-04-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |